Strength comparision in Systemverilog

`define compSigValues(sig_a, sig_b)\
  begin\
  string sig_a_strength, sig_b_strength;\
  sig_a_strength = $sformatf("%v", sig_a);\
  sig_b_strength = $sformatf("%v", sig_b);\
  if ( sig_a_strength == sig_b_strength) begin\
    $display("Signal values %s and %s match", sig_a_strength, sig_b_strength);\
  end\
  else begin\
    $display("Signal values %s and %s don't match", sig_a_strength, sig_b_strength);\
  end\
 end

module top ();
  wire a, b;
  wire c, d;

  assign (strong1, strong0) a = 1;
  assign (pull1, pull0)     b = 1;
  assign (weak1, weak0)     c = 1;
  assign (weak1, weak0)     d = 1;

  initial begin
    #5;
    $display("comparision of a, b");
    `compSigValues(a, b)

    $display("comparision of c, d");
    `compSigValues(c, d)
  end
endmodule
 

Output:

comparision of a, b

Signal values St1 and Pu1 don't match

comparision of c, d

Signal values We1 and We1 match