Verification Engineer's Blog

I am a Verification Engineer at Intel. I started the Verification blog to store solutions to small (and big) problems I've faced in my day to day work. I want to share them with the community in the hope that they may be useful to someone else.

Wednesday, 1 July 2015

uvm_do/ovm_do vs start_item/finish_item

uvm_do/ovm_do



start_item/finish_item


Reference: 
1) uvm_sequence_defines.svh
2) uvm_sequence_base.svh
Posted by Sagar Shah No comments:
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Labels: ASIC, finish_item, OVM, ovm_do, start_item, uvm_do, verification
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