Difference between wire, reg and logic in SystemVerilog

Wire:-

1.     Wires are used for connecting different elements
2.     They can be treated as a physical wire
3.     They can be read or assigned
4.     No values get stored in them
5.     They need to be driven by either continuous assign statement or from a port of a module

Reg:-

1.     Contrary to their name, regs doesn't necessarily corresponds to physical registers
2.     They represents data storage elements in Verilog/SystemVerilog
3.     They retain their value till next value is assigned to them (not through assign statement)
4.     They can be synthesized to FF, latch or computational circuit (They might not be synthesizable !!!)

Wires and Regs are present from Verilog time-frame. SystemVerilog added a new data type called logic to them. So the next question is what is this logic data type and how it is different from our good old wire/reg.

Logic:-

    As we have seen, reg data type is bit mis-leading in Verilog. SystemVerilog's logic data type addition is to remove the above confusion. The idea behind having a new data type called logic which at least doesn't give an impression that it is hardware synthesizable

    Logic data type doesn't permit multiple driver. It has a last assignment wins behavior in case of multiple assignment (which implies it has no hardware equivalence). Reg/Wire data type give X if multiple driver try to drive them with different value. Logic data type simply assign the last assignment value.

The next difference between reg/wire and logic is that logic can be both driven by assign block, output of a port and inside a procedural block like this

	logic a;
	assign a = b ^ c; // wire style
	always (c or d) a = c + d; // reg style
	MyModule module(.out(a), .in(xyz)); // wire style

view raw wire_reg_logic.sv hosted with ❤ by GitHub

Barrier in UVM and Usage of uvm_barrier

uvm_barrier can be used to force a set of independently executing processes (e.g. virtual sequences) to wait until they have all reached a particular point.
The barrier provides a flexible synchronization mechanism between the processes: its threshold can be programmed to set the number of processes that must reach the synchronization point before the barrier is 'lifted'.

A barrier is like a semaphore in reverse. It simply blocks until a threshold number of requests.

The uvm_barrier class provides a multi-process synchronization mechanism.  It enables a set of processes to block until the desired number of processes get to the synchronization point, at which time all of the processes are released.

APIs of uvm_barrier class

1. wait_for : Waits for enough processes to reach the barrier before continuing. 
2. reset : Resets the barrier. This sets the waiter count back to zero. 
3. set_auto_reset : Determines if the barrier should reset itself after the threshold is reached. Default is on 
4. set_threshold : Sets the process threshold. 
5. get_threshold : Gets the current threshold setting for the barrier. 
6. get_num_waiters : Returns the number of processes currently waiting at the barrier. 
7. cancel : Decrements the waiter count by one. This is used when a process that is waiting on the barrier is killed or activated by some other means.

Consider following examples,

	module top();
	import uvm_pkg::*;
	uvm_barrier b;
	task delay(
	input uvm_barrier _b,
	input int unsigned _delay,
	input string _name
	);
	automatic string _s = _name;
	#_delay;
	_b.wait_for();
	$display("%s Process @%0t", _s, $realtime);
	endtask : delay
	initial begin
	b = new("Barrier",2); // Wait for 2 process to be completed
	fork
	delay(._b(b), ._delay(10), ._name("A"));
	delay(._b(b), ._delay(35), ._name("B"));
	delay(._b(b), ._delay(50), ._name("C"));
	delay(._b(b), ._delay(20), ._name("D"));
	delay(._b(b), ._delay(80), ._name("E"));
	delay(._b(b), ._delay(70), ._name("F"));
	join
	$display("outside Fork-Join @%0t", $realtime);
	end
	endmodule
	//Output:
	// A Process @20
	// D Process @20
	// B Process @50
	// C Process @50
	// F Process @80
	// E Process @80
	// outside Fork-Join @80

view raw uvm_barrier_ex1.sv hosted with ❤ by GitHub

	module top();
	import uvm_pkg::*;
	uvm_barrier b;
	task delay(
	input uvm_barrier _b,
	input int unsigned _delay,
	input string _name
	);
	automatic string _s = _name;
	#_delay;
	_b.wait_for();
	$display("%s Process @%0t", _s, $realtime);
	endtask : delay
	initial begin
	b = new("Barrier",3); // Wait for 3 process to be completed
	fork
	delay(._b(b), ._delay(10), ._name("A"));
	delay(._b(b), ._delay(35), ._name("B"));
	delay(._b(b), ._delay(50), ._name("C"));
	delay(._b(b), ._delay(20), ._name("D"));
	delay(._b(b), ._delay(80), ._name("E"));
	delay(._b(b), ._delay(70), ._name("F"));
	join
	$display("outside Fork-Join @%0t", $realtime);
	end
	endmodule
	//Output:
	// D Process @35
	// A Process @35
	// B Process @35
	// F Process @80
	// C Process @80
	// E Process @80
	// outside Fork-Join @80

view raw uvm_barrier_ex2.sv hosted with ❤ by GitHub

Difference between setenv and set in csh

To findout difference between set and setenv first look at below example.

	[sagar.shah@~]$ cat csh_script.csh
	#!/bin/csh
	echo $a;
	[sagar.shah@~]$ csh csh_script.csh
	a: Undefined variable.
	[sagar.shah@~]$ set a=5
	[sagar.shah@~]$ echo $a
	5
	[sagar.shah@~]$ csh csh_script.csh
	a: Undefined variable.
	[sagar.shah@~]$ setenv a 10
	[sagar.shah@~]$ csh csh_script.csh
	10
	[sagar.shah@~]$ echo $a
	5

view raw set_vs_setenv.csh hosted with ❤ by GitHub

So, from above example, it can be conclude that set is setting a variable ,which has scope only to that terminal. Variable using set has no scope in scripts running from that terminal.

setenv has scope in terminal as well as in running scripts from that terminal. But any variable with same name is setting using set command and setenv command then set command is overwrite the value of that variable for terminal, but from scripts only variables using setenv can be access.

So, set has visibility only to terminal and can't be access from scripts.
setenv has visibility to both to terminal  and scripts, but set has more priority than setenv for terminal.

How to Format Source Code in Blogger

I had a problem embedding code snippets and inline code examples to my blog. I surfed and found a simple solution as below:

• Using https://gist.github.com/

1. Create an account on github.com
2. After logging in to github, click on Gist
3. Add a file-name with an extension (extension will be used to add syntax highlighting)
4. Add your code snippet which need to be added to your blog post
5. Click “Create Public Gist” button at the button
6. Click on the “embed” link and copy the script generated
   
   
   This is all from Gist side. Now to Blogger,
   
   
   
   1. Paste the script where you need to add the code snippet
   2. Make sure to select the option “Interpret typed HTML” under Post Options -> Compose Settings

•  Using http://hilite.me/

• Using http://codeformatter.blogspot.in/2009/06/about-code-formatter.html