Default timeout for simulation or you can say timeout for run_phase (as rest all phases are non-time consuming) is `UVM_DEFAULT_TIMEOUT, if not overridden by uvm_root::set_timeout or uvm_cmdline_processor::+UVM_TIMEOUT.
Default value of `UVM_DEFAULT_TIMEOUT is 9200 second.
Default value of `UVM_DEFAULT_TIMEOUT is 9200 second.
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Example 1 (Timeout at default time which is 9200 second):
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1) Overridden by uvm_root::set_timeout
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Example 2 (Timeout at specified time which is specified using set_timeout):
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2) Overridden by uvm_cmdline_processor::+UVM_TIMEOUT
+UVM_TIMEOUT=, allows users to change the global timeout of the UVM framework. The argument (‘YES’ or ‘NO’) specifies whether user code can subsequently change this value. If set to ‘NO’ and the user code tries to change the global timeout value, a warning message will be generated.
Example 3 (Timeout at 100s using simulation switch +UVM_TIMEOUT=100000000000):
Note: Here you need to give simulation time in format of timescale defined in simulation
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If i call uvm_top::set_timeout() and at the same time used the plusarg +UVM_TIMEOUT which one will take effect?
ReplyDeleteIt depends on when you call set_timeout.
Delete+UVM_TIMEOUT is evaluated in build_phase of uvm_root class.
And here I have called set_timeout() in start_of_simulation_phase so set_timeout() will override timeout set by +UVM_TIMEOUT.
is +UVM_TIMEOUT is alternative to $finish?
ReplyDeleteNo. If it does timeout, it will be a UVM_FATAL failure.
DeleteHi Sagar, in my testbench environment there is no raise/drop objection any where, so my simulation ended at @0ns, but i want to control the simulation without ending @0ns ,any solution for that, could you please help on this
ReplyDelete