Sunday, 17 April 2016

Coverage FAQ

What do you mean by coverage?
Coverage is used to check whether the Test-bench has satisfactory exercised the design or not.

What are the different types of coverage available in SV?
Code coverage:
Measure of how much of the design code has been exercised
Functional Coverage:
Measures how much of the design specification, as defined in the test plan, has been exercised.
It is used as a reference or possible functional verification closure criteria.
It is user-specified and is not automatically generated from the design.
It is based on the design specification.

What is the name of method in which covergroup is constructed in your project?
Constructor of coverage class.

Different ways of sampling coverage:
1. Use clock to sample covergroup
      covergroup cg @ (posedge clk)
2. Use any event of variable to sample covergroup 
      event ev; covergroup cg @ ev
      bit var; covergroup cg @ var;
3. Call the built-in sample() method.
      covergroup cg; cg cg_inst = new(); cg_inst.sample();
4. Call the explicit sample() method
       covergroup cg wth function sample (bit a);

What are the different types of Code coverage?
1.    Line,
2.    Block,
3.    Conditional,
4.    Branch,
5.    FSM,
          State coverage
          Transition coverage
6.    Toggle,
7.    Path,

What is the difference between code coverage and functional coverage?
Code coverage will give information about how many lines are executed, how many times expressions, branches executed. It doesn't know anything about what design supposed to do. This coverage is collected by the simulation tools. Users use this coverage to reach those corner cases which are not hit by the random test-cases. Users have to write the directed test-cases to reach the missing code coverage areas.

Functional coverage, by the name it-self is related to the functionality of the design and it is defined by the user. User will define the coverage points for the functions to be covered in DUT. This is completely under user control.

Which coverage has more importance, code coverage or functional coverage?
Both of them have equal importance in the verification. Verification engineers will consider both coverage to measure the verification progress.
Even if a feature is not implemented in design, code coverage can report 100% coverage.

If code coverage is 100% and functional coverage is not, then what does it mean?
Reason could be any one of the following,
1) There could be a bug in the functional coverage block which is not recording the execute scenario User need to debug to find and fix the issue.
2) User did not exercise all the scenarios. User need to write test-cases to fill the functional coverage holes.
3) Even if a feature is not implemented in design, code coverage can report 100% coverage, but functional does not.

If functional coverage is 100% and code coverage is not, then what does it mean?
1) The functional coverage will hot due to faulty pass but some of the DUT code may not get exercised.
2) If DUT is a configurable IP, it may has some use less code to support additional functionality, due to this code coverage will not be achieved 100%.
3) RTL designer add a code for new feature, but due to miscommunication between designer and verification engineer, when verification engineer did code coverage, he didn’t get 100% code coverage.

What is the difference between ignore bins and illegal bins?
When ignore bin hits then tool will not give any warning/error, but when illegal bin hits then tool will give Tool Error (which is not a SystemVerilog Error ($error), it's a Tool Error).

If illegal bin hits then how to resolve that issue?
If illegal bins hits that means issue is in Generation, so need to modify/update generation logic by putting additional Constraint.

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