SystemVerilog FAQ3

Write a clock generator without using always block.

initial begin

  clk <= '0;

  forever #(CYCLE/2) clk = ~clk

end




What is the difference between program block and module?

1. Program blocks can't have always block inside them, modules can have.

2. Program blocks can't contain UDP, modules, or other instance of program block inside them. Modules don't have any such restrictions.

3. Inside a program block, program variable can only be assigned using blocking assignment and non-program variables can only be assigned using non-blocking assignments. No such restrictions on module.

4. Program blocks get executed in the re-active region of scheduling queue, module blocks get executed in the active region

Why always block is not allowed in program block? 

In a design, an always block might trigger on every positive edge of a clock from the start of simulation. A test-bench, on the other hand, goes through initialization, drive and respond to design activity, and then completes. When the last initial block completes, simulation implicitly ends just as if you had executed $finish. If you had an always block, it would never stop, so you would have to explicitly call $exit to signal that the program block completed.

How to implement always block logic in program block?

Using forever loop.

Convert below always block’s logic using forever loop.

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	// Logic with always
	always @(posedge clk or negedge reset_) begin
	if(!reset_) begin
	data <= '0;
	end else begin
	data <= data_next;
	end
	end
	// Logic with Forever
	forever begin
	fork
	begin : reset_logic
	@ (negedge reset_);
	data <= '0;
	end : reset_logic
	begin : clk_logic
	@ (posedge clk);
	if(!reset_) data <= '0;
	else data <= data_next;
	end : clk_logic
	join_any
	disable fork
	end

view raw always_forever.sv hosted with ❤ by GitHub

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