Saturday, 23 April 2016

rand_mode and constraint_mode in System Verilog



rand_mode:

The random nature of variables declared as rand or randc can be turned on or off dynamically by using in-built method called rand_mode().  rand_mode() can be called as function or task.

In below example, rand_mode of all variable of class is disabled and enabled.
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We can also change rand_mode of specific variable. Consider below example,
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When rand_mode method is called as function, it returns the active status of the specified random variable.
When called as a function, rand_mode() returns the current active state of the specified random variable. It returns 1 if the variable is active (ON) and 0 if the variable is inactive (OFF).
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A compiler error shall be issued if the specified variable does not exist within the class hierarchy or even though it exists but not declared as rand or randc. The following example illustrates the second case.

rand_mode of rand static variable,
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constraint_mode


SystemVerilog supports to change the status of constraint block dynamically.
The constraint_mode() method can be used to active/inactive constraint. By default all the constraint blocks are active. When a constraint is inactive, it is not considered by the randomize() method.

It can be used as task or function.
When called as a task, the argument to the constraint_mode task method determines the operation to be performed. 
When called as a function, constraint_mode() returns the current active state of the specified constraint block. It returns 1 if the constraint is active (ON) and 0 if the constraint is inactive (OFF).

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