I am a Verification Engineer at Cadence Design System. I started the Verification blog to store solutions to small (and big) problems I've faced in my day to day work. I want to share them with the community in the hope that they may be useful to someone else.
Saturday, 16 April 2016
Write a clock generator without using always block.
clk <= '0;
forever #(CYCLE/2) clk = ~clk
is the difference between program block and module?
blocks can't have always block inside them, modules can have.
blocks can't contain UDP, modules, or other instance of program block inside
them. Modules don't have any such restrictions.
a program block, program variable can only be assigned using blocking
assignment and non-program variables can only be assigned using non-blocking
assignments. No such restrictions on module.
blocks get executed in the re-active region of scheduling queue, module blocks
get executed in the active region
Why always block is not allowed in program block?
a design, an always block might trigger on every positive edge of a clock from
the start of simulation. A test-bench, on the other hand, goes through
initialization, drive and respond to design activity, and then completes. When
the last initial block completes, simulation implicitly ends just as if you had
executed $finish. If you had an always block, it would never stop, so you would
have to explicitly call $exit to signal that the program block completed.
How to implement always block logic in program block?
Using forever loop.
Convert below always block’s logic using forever loop.