Streaming Operator in System Verilog

class transaction;

  bit [7:0] addr;
  bit [7:0] csm;
  bit [7:0] data;

  function void pack(ref bit [23:0] bytes[$]);
    bytes = { >> {addr, csm, data}};
  endfunction : pack
 
  function void unpack(ref bit [23:0] bytes[$], ref transaction tr);
    { >> {tr.addr, tr.csm, tr.data}} = bytes;
  endfunction : unpack

endclass : transaction

module top();
  transaction tr;
  transaction tr2;
  bit [23:0] bytes[$];

  initial begin
    tr = new();
    tr.addr = 8'hFF;
    tr.csm  = 8'hAA;
    tr.data = 8'h55;
    void '(tr.pack (bytes));
    foreach (bytes[i])
    begin
      $display("bytes[%0d]=%0h", i, bytes[i]);
    end

    tr2 = new();
    tr.unpack(bytes, tr2);
    $display("tr2 : addr=%h, csm=%h, data=%h", tr2.addr, tr2.csm, tr2.data);
  end
endmodule : top

//Output:
//  bytes[0]=ffaa55
//  tr2 : addr=ff, csm=aa, data=55