I am a Verification Engineer at Cadence Design System. I started the Verification blog to store solutions to small (and big) problems I've faced in my day to day work. I want to share them with the community in the hope that they may be useful to someone else.
Friday, 5 February 2016
How to change verbsity for particular component in UVM
There are two ways to set/control/change verbosity of particular component.