import vs `include in SystemVerilog

The compiler goes through a pre-processor step. This step processes all the include files, conditionals, and text macros into a single stream of text. Except for error reporting and debugging, the compiler does not care how many files were used to make up that stream of text.

`include directive is just a mechanism for assembling text. The directive provides two key pieces of functionality:

• Maintain repetitive blocks of text in a single file,
• Specify file compilation order dependences from within a file instead of on the compiler command line,

SystemVerilog also supports separate compilation units. A compilation unit is one stream of text.

If you have multiple compiler command lines, then you will have at least one compilation unit per command line.

If you have multiple compilation units and have a set of classes that need to be shared across the compilation units, then you must use a package to define those classes or any user defined type.

And then in other compilation you can access that set of classes by importing that package.

Let’s go through one example,

1. Include

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After `including class A into each package, you wind up with two definitions of class A. Using `include is just a shortcut for cut and pasting text in a file. Importing a name from a package does not duplicate text; it makes that name visible from another package without copying the definition.

2. Import

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Class A is declared in package P, and only in package P. The variables R::a1 and S::a1 are type compatible because they are both of type P::A. The fact that class A was `included from another file once it is expanded is no longer relevant once you consider the placement of the text from the file.

Reference:

1. https://verificationacademy.com/forums/ovm/do-you-include-or-import

2. https://blogs.mentor.com/verificationhorizons/blog/2010/07/13/package-import-versus-include