`define macro usage in SystemVerilog

It's not possible to use a `define macro within a string literal. According to the SystemVerilog LRM: Macro substitution and argument substitution shall not occur within string literals

Let’s go through below example to understand it in detail,

 ---------------------------------------------------------------------------

 ---------------------------------------------------------------------------

However a string literal can be constructed by using a macro that takes an argument and including the quotes in the macro by using `".

According to SystemVerilog LRM: An `" overrides the usual lexical meaning of " and indicates that the expansion shall include the quotation mark, substitution of actual arguments, and expansions of embedded macros. This allows string literals to be constructed from macro arguments.

 ---------------------------------------------------------------------------

 ---------------------------------------------------------------------------

Now what if you want to add double quotes in string which is constructed using macro. SystemVerilog provides support for that.

A `\`" indicates that the expansion should include the escape sequence \".

Let’s go through example to see how it works,

 ---------------------------------------------------------------------------

 ---------------------------------------------------------------------------

 SystemVerilog LRM also provides support to construct identifier from arguments using ``.

There are three places where we can substitute argument to construct identifier

1) Substitute argument in between something (neither at the end nor at the beginning of the identifier)

2) Prepend argument (at the beginning of the identifier)

2) Append argument (at the end of the identifier)

 ---------------------------------------------------------------------------

 ---------------------------------------------------------------------------

Reference:

1) SystemVerilog 2012 LRM