Why phasing is used? What
are the different phases in uvm?
UVM Phases is used to
control the behavior of simulation in a systematic way & execute in a
sequential ordered to avoid race condition. This could also be done in system
verilog but manually.
Which phases of UVM are Top-Down?
build_phase() & final_phase() are Top-Down, rest all phases are Bottom-Up.
Which phases of UVM are task?
run_phase(),pre_reset_phase(), reset_phase(), post_reset_phase(),
pre_configure_phase(), configure_phase(), post_configure_phase(),
pre_main_phase(), main_phase(), post_main_phase(),
pre_shutdown_phase(), shutdown_phase(), post_shutdown_phase()
How do uvm phases initiate?
Calling run_test() constructs the UVM
environment root component and then initiates the UVM phasing.
Why is the build_phase() in
UVM executed in a Top - Down fashion and the other phases in Bottom - Up
fashion?
The build phase has to be
that way because the parent component's build_phase constructs the child
components. You couldn't call the child's build_phase before the parent's
build_phase because they the child objects haven't been constructed yet. You
need a constructed object to call its method.
The build_phase() is also
executed top-down so that the parent can provide override setting that the
children will use when they execute their build_phase()
The ordering within the
other phases should not matter, except you might want know that the top level's
report_phase comes last.
What is the order of
execution of run_phase() ?
The run_phase() of each
component is executed concurrently with no defined order you can depend on.
During the run_phase() is there
something like super.run_phase(phase) called?
You only need to call
super.method() if you are extending a class an need the functionality of the
base method. There is nothing inside the run_phase() of a uvm_component, so
there is no need to call super.run_phase() when extending from it.
You may want to call it when
extending your classes from your base classes.
What
is the difference between run_phase and main_phase in uvm_component?
Actually,
you can start a sequence in any phase. It is more important to understand the
domain/scheduling relationships between the task based (i.e. runtime) phases.
UVM undergoes a number of pre-simulation phases (build, connect,
end_of_elaboration, start_of_simulation) that are all implemented with
functions. Once those are completed, the task based phases begin.
The standard
includes two schedules.
- One is simply the run_phase, which starts executing at time zero and continues until all components have dropped their objections within the run_phase.
- The other schedule contains twelve phases that execute parallel to the run phase. They are: pre_reset, reset, post_reset, pre_config, config, post_config, pre_main, main, post_main, pre_shutdown, shutdown, and post_shutdown. They execute in sequence.
Every component has the opportunity to define or not
define tasks to execute these phases. A phase starts only when all components
in the previous phase have dropped their objections. A phase continues to
execute until all components have dropped their objections in the current
phase.
Why connect_phase() is
bottom-up?
