Thursday, 7 January 2016

OOPS Interview Questions.

What is OOPS?

OOPS is abbreviated as Object Oriented Programming system
It is a programming language model organized around objects rather than "actions" and data rather than logic.
Programming approach that provided modularity means both data_members (attributes) and methods (function or task) can be used as templates for creating copies of such modules on demand.

 

What are the Basic Concepts of OOPs?

  1. Abstraction.
  2. Encapsulation.
  3. Inheritance.
  4. Polymorphism.

 

What is an object?

An object is a variable of user defined data type class.
Or,
Object is an instance of a class that is created dynamically.

 

What is Abstraction?

Abstraction refers to the process of representing only essential or relevant data to the users without showing unnecessary or background information.
Users just need to give appropriate arguments to the method while using it, internal complexity or background process is not shown to users. They get the result what they want.
Since class is a concept of data abstraction, it is known as abstract data type (ADT).

 

What is Encapsulation?

Prevents the data from unwanted access by binding of code and data in a single unit called object/class.
Or,
The wrapping up of data & methods into a single unit (called class) is known as encapsulation. Here class acts like a container.
These methods provide interface between program and object/class’s data. The insulation of data from direct access by the program is called data hiding. (Keep in mind that all data_member are declared as private)

 

What is Inheritance?

Promotes the re-usability of code and eliminates the use of redundant code.
Inheritance allows a Child class to inherit properties (member, method) from its parent class.
Only properties with access modifier public (local keyword in sv) and protected (protected keyword in sv) can be accessed in child class. (by default all properties are public)
In SystemVerilog this is achieved by using extends keyword.

 

What is multiple inheritance?

Multiple inheritance refers to a feature of some object-oriented programming languages in which a class can inherit properties from more than one class.
Systemverilog doesn’t support multiple inheritance. To overcome this problem it allows to implement multiple interface-class.

 

Is it possible for a class to inherit the constructor of its base class?

No, a class cannot inherit the constructor of its base class.

 

Can you call a base class method without creating instance?

Yes. But,
  • It’s possible if it’s a static method.
  • It’s possible if you derive the class from base class then take instance of derived class when call method by using derived class’s instance.
  • It’s possible from derived classes using keyword “super”.

 

What is polymorphism?

The ability to define a method in multiple forms is called Polymorphism.
In systemverilog there are two types of polymorphism:
  1. Compile time polymorphism (overloading) and
  2. Runtime polymorphism (overriding).
Overloading:
When a class has more than one method with same name but different parameters, then we call those methods are overloaded.
Overloaded methods will have same name but different number of arguments or different types of arguments or both.
Overloaded methods can be either static or non-static.

However System Verilog doesn't support Method Overloading (except constructor).

Overriding:
Language feature that allows a subclass or child class to provide a specific implementation of a method that is already provided by one of its super class or parent class.
Actual method which will be called is determined by the type of object at run-time.
Static methods cannot be overridden.
Two virtual methods must have the same signature.

 

What are the rules to be followed while overriding a method?

  • Name of the method must be same,
  • Return type of method must be same,
  • Parameter list of a method must be same,
  • Must not reduce the visibility.

 

What is method signature? What are the things it consists of?

Method signature is used by the compiler to differentiate the methods. Method signature consists of three things.
  • Method name
  • Number of arguments
  • Types of arguments

 

Virtual vs pure_virtual?

Virtual: If you forgot to override method in child class then at run-time, parent class’s method will be executed. If your parent class’s method is empty, then nothing will happen and even you will not get any warning/error for that. This will leads to unexpected behavior of code.
Pure virtual: If you forgot to override method in child class then at compile-time error will be shouted. So, you will come to know that you forgot to override that particular method in child class. This will stop unexpected behavior of code.
Pure virtual method is also called as abstract method.

 

What is abstract class?

An abstract class is a class that is declared as a virtual class.
Abstract classes are those which can be used for creation of handles. However their methods and constructors can be used by the child or extended class. The need for abstract classes is that you can generalize the super class from which child classes can share its methods.
A class is called abstract class if it is only used as a super-class for other classes.
Derived classes must define the properties of abstract class.
Abstract classes cannot be instantiated.
The subclass of an abstract class which can create an object is called as "concrete class".

 

Explain the concept of constructor?

Constructor is a special method of a class, which is called automatically when the instance of a class is created. It is created with the same name as the class and initializes all class members, whenever you access the class. The main features of a constructor are as follows:
  • Constructors do not have any return type.
  • Constructors can be overloaded.
  • It is not mandatory to declare a constructor; it is invoked automatically.

Tuesday, 29 December 2015

Callback in SystemVerilog

One of the main guidelines of this book is to create a single verifi cation environment that you can use for all tests with no changes. The key requirement is that this testbench must provide a “hook” where the test program can inject new code without modifying the original classes.

Your driver may want to do the following:
  • Inject errors
  • Drop the transaction
  • Delay the transaction
  • Put the transaction in the scoreboard
  • Gather functional coverage data
Rather than try to anticipate every possible error, delay, or disturbance in the flow of transactions, the driver just needs to “call back” a method that is defined in the top-level test.
The beauty of this technique is that the callback method can be defined differently in every test. As a result, the test can add new functionality to the driver using callbacks, without editing the Driver class.
For some drastic behaviors such as dropping a transaction, you need to code this in the class ahead of time, but this is a known pattern. The reason why the transaction is dropped is left to the callback.

As shown in "Developer code" the Driver::run task loops forever with a call to a transmit task. Before sending the transaction, run calls the pre-transmit callback, if any. After sending the transaction, it calls the post-callback task, if any. By default, there are no callbacks, so run just calls transmit.



You could make Driver::run a virtual method and then override its behavior in an extended class, perhaps MyDriver::run. The drawback to this is that you might have to duplicate all the original method’s code in the new method if you are injecting new behavior. Now if you made a change in the base class, you would have to remember to propagate it to all the extended classes. Additionally, you can inject a callback without modifying the code that constructed the original object.

A callback task is created in the top-level test and called from the driver, the lowest level of the environment. However, the driver does not have to have any knowledge of the test – it just has to use a generic class that the test can extend.
 


Limitations of SystemVerilog callback (w.r.t. uvm_callback).
  • You cannot control particular nth number of transaction. Callback affects all the transaction or in random manner if you use randomization in extended callback as I had used in above both examples. For example you want initial some (n) transcation to drive without any modification, then for particular (n+1) transaction you want to modified its content. Then again for rest of all transaction you don't want any modification. This is not possible with SystemVerilog callback.
  • You cannot Add or Delete callback runtime.

Monday, 28 December 2015

Difference between Variable and Signal in VHDL

Scope wise:
SIGNAL has scope to whole architecture. It can be access from any place in architecture of enitity.
VARIABLE is local t procedure defined in the architecture.

Behavior wise:
Variable assignment is evaluated and assigned in a single step:
1) Execution flow within the procedure is blocked until the Execution flow within the procedure is blocked until the
assignment is completed.
Variable assignment is same as Blocking assignment in Verilog.

Signal assignment is Evaluated and assigned in two steps:
1) The right The right-hand side is evaluated immediately.
2) The assignment to the left-hand side is postponed until other evaluations in the current time step are completed other evaluations in the current time step are completed.
Execution flow within the procedure continues until a timing control is encountered (flow is not blocked)
Signal assignment is same as Non-Blocking assignment in Verilog.
If several values are assigned to a given signal in one process, only the last assignment is effective.

Synthesis wise:
SIGNAL inter a FLOP during synthesis.
VARIABLE infer just a WIRE during synthesis.

Example:

Signal assignment:


Variable assignment:

UVM_ERROR demoter code


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Package in SystemVerilog

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Eighth Example: (package and module having variable with same name)
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Ninth Example: (package and module having variable with same name)
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