Difference between Variable and Signal in VHDL

Scope wise:
SIGNAL has scope to whole architecture. It can be access from any place in architecture of enitity.
VARIABLE is local t procedure defined in the architecture.

Behavior wise:
Variable assignment is evaluated and assigned in a single step:
1) Execution flow within the procedure is blocked until the Execution flow within the procedure is blocked until the
assignment is completed.
Variable assignment is same as Blocking assignment in Verilog.

Signal assignment is Evaluated and assigned in two steps:
1) The right The right-hand side is evaluated immediately.
2) The assignment to the left-hand side is postponed until other evaluations in the current time step are completed other evaluations in the current time step are completed.
Execution flow within the procedure continues until a timing control is encountered (flow is not blocked)
Signal assignment is same as Non-Blocking assignment in Verilog.
If several values are assigned to a given signal in one process, only the last assignment is effective.

Synthesis wise:
SIGNAL inter a FLOP during synthesis.
VARIABLE infer just a WIRE during synthesis.

Example:

Signal assignment:

	library IEEE;
	use IEEE.std_logic_1164.all;
	entity xor_sig is
	port (
	A, B, C: in STD_LOGIC;
	X, Y: out STD_LOGIC
	);
	end xor_sig;
	architecture SIG_ARCH of xor_sig is
	signal D: STD_LOGIC;
	signal E: STD_LOGIC;
	signal F: STD_LOGIC;
	begin
	SIG:process (A,B,C)
	begin
	D <= A; -- ignored !!
	E <= D xor F; -- OLD value of D is taken for right-hand side evaluation.
	F <= B xor D; -- OLD value of D is taken for right-hand side evaluation.
	X <= C xor E; -- OLD value of E is taken for right-hand side evaluation.
	D <= B; -- overrides !! After this timestamp value of D is equal to B.
	Y <= D xor F; -- OLD value of both D and F is taken for right-hand side evaluation.
	-- (During this assignment D don't has value of A or B)
	end process;
	end SIG_ARCH;

view raw vhdl_signal_vs_variable_1.vhd hosted with ❤ by GitHub

Variable assignment:

	library IEEE;
	use IEEE.std_logic_1164.all;
	use IEEE.std_logic_unsigned.all;
	entity xor_var is
	port (
	A, B, C: in STD_LOGIC;
	X, Y: out STD_LOGIC
	);
	end xor_var;
	architecture VAR_ARCH of xor_var is
	begin
	VAR:process (A,B,C)
	variable D: STD_LOGIC;
	variable E: STD_LOGIC;
	variable F: STD_LOGIC;
	variable P: STD_LOGIC;
	variable Q: STD_LOGIC;
	begin
	D := A; -- D is assigned with value of A.
	E := D xor F; -- NEW value of D is taken for right-hand side evaluation. (D has value of A)
	F := B xor D; -- NEW value of D is taken for right-hand side evaluation. (D has value of A)
	P := C xor E; -- NEW value of E is taken for right-hand side evaluation.
	D := B; -- Again value of D is changed. D is assigned with value of B.
	Q := D xor F; -- NEW value of both D and F is taken for right-hand side evaluation.
	-- (D has value of B, F has value of (B xor D(=A)))
	X <= P;
	Y <= Q;
	end process;
	end VAR_ARCH;

view raw vhdl_signal_vs_variable_2.vhd hosted with ❤ by GitHub