Wednesday, 16 December 2015

Randcase in SystemVerilog

randcase is a case statement that randomly selects one of its branches.
Randcase can be used in class or modules.
The randcase item expressions are non-negative integral values that constitute the branch weights.
An item weight divided by the sum of all weights gives the probability of taking that branch.

For example:

The sum of all weights is 8; therefore, the probability of taking the first branch is (3/8)0.375, the probability

of taking the second is (1/8)0.125, and the probability of taking the third is (4/8)0.5.

If a branch specifies a zero weight, then that branch is not taken.
If all randcase_items specify zero weights, then no branch is taken and a warning can be issued.

The randcase weights can be arbitrary expressions, not just constants.

For example:

In the preceding example, the first three weight expressions are computed using 8-bit precision, and the fourth

expression is computed using 12-bit precision.
The resulting weights are added as unsigned values using 12-bit precision. The weight selection then uses unsigned

12-bit comparison.

Each call to randcae statement will return a random number in the range from 0 to SUM.
$urandom_range(0,SUM) is used to generate a random number.

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