Tuesday, 2 February 2016
Advantages of UVM
UVM is a SystemVerilog class library explicitly designed to help you build modular reusable verification components and test-benches. It is an industry standard so you can acquire UVM IP from other sources and use them in your environment. If you don't use UVM, you'll have to build everything yourself from scratch.
Sequence methodology gives good control on stimulus generation. There are several ways in which sequences can be developed which includes randomization, layered sequences, virtual sequences etc which provides a good control and rich stimulus generation capability.
Separating stimulus generation from Test-benches – Tests in terms of stimulus/sequences are kept separate from the actual test-bench hierarchy and hence there can be reuse of stimulus across different units or across projects.
Factory mechanisms simplifies modification of components easily. Creating each components using factory enables them to be overridden in different tests or environments without changing underlying code base.
Configuration management: Config mechanisms simplify configuration of objects with deep hierarchy. The configuration mechanism helps in easily configuring different test-bench components based on which verification environment uses it and without worrying about how deep any component is in test-bench hierarchy.
Modularity and Re-usability (using TLM over mailbox) – The methodology is designed as modular components (Driver, Sequencer, Agents, Env etc.) Which enables reusing components across unit level to multi-unit or chip level verification as well as across projects.
Advantages of TLM over mailbox:
Let's say you have two components: A and B. Component A has a thread doing puts and component B has a thread doing gets. They are both connected through a common mailbox which means they both must declare handles to a matching mailbox type. This creates an unwanted dependency. At some point, I might want some other component other than a mailbox to connect to, like some kind of arbitrator. So I would have to modify the handles types in the components.