Thursday, 23 March 2017

Automatic raise/drop objection with UVM-1.2

Variable uvm_sequence_base::starting_phase is deprecated and replaced by two new methods set_starting_phase and get_starting_phase, which prevent starting_phase from being modified in the middle of a phase. This change is not backward-compatible with UVM 1.1, though variable starting_phase, although deprecated, has not yet been removed from the base class library.

New method uvm_sequence_base::set_automatic_phase_objection causes raise_objection and drop_objection to be called automatically around a sequence, avoiding the need to call raise/drop_objection manually in one common situation.

Lets understand it trough below mentioned example.
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Ref:
1) https://www.doulos.com/knowhow/sysverilog/uvm/uvm-1.2/

3 comments:

  1. Thanks for sharing this wonderful and useful information,Please keep updating.

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  2. Hi Sagar what is the need to do set_starting_phase , we are in run_phase already why do we do set and get starting phase?

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