Kill process in SystemVerilog using "disable fork" and "disable LABEL"

Most of us, have faced these some issues at least one time in our SystemVerilog programming while using "disable fork" and "disable LABEL".

Let's first go through below example,
------------------------------------------------------------------------------

	class abc;
	string name;
	task multiple_process(input int unsigned delay);
	fork
	begin
	forever begin
	#20;
	$display ($time, " %s, Process:1", name);
	end
	end
	join_none
	fork
	begin
	#delay;
	$display ($time, " %s, Process:2", name);
	end
	begin
	#10;
	$display ($time, " %s, Process:3", name);
	end
	join_any
	disable fork;
	$display ($time, " %s, multiple_process completed", name);
	endtask : multiple_process
	endclass : abc
	module top1();
	abc a1, a2;
	initial begin
	a1 = new();
	a1.name = "a1";
	a2 = new();
	a2.name = "a2";
	fork
	a1.multiple_process(5);
	a2.multiple_process(7);
	join
	#30 $finish;
	end
	endmodule : top1
	//Output:
	// 5 a1, Process:2
	// 5 a1, multiple_process completed
	// 7 a2, Process:2
	// 7 a2, multiple_process completed

view raw disable_process_1.sv hosted with ❤ by GitHub

------------------------------------------------------------------------------

As shown in above example, "Process:1" is running continuously. Two different processes, "Process:2" and "Process:3" should run in parallel and any of two processes is completed, other process shall stop its execution due to join_any statement.

While simulating above code, you may face that when the disable fork is executed, "Process:1" also stop it's execution. So, to avoid this kind of situation, it's better to use "disable LABEL" statement.
------------------------------------------------------------------------------

	class abc;
	string name;
	task multiple_process(input int unsigned delay);
	fork
	begin
	forever begin
	#20;
	$display ($time, " %s, Process:1", name);
	end
	end
	join_none
	fork : LABLE
	begin
	#delay;
	$display ($time, " %s, Process:2", name);
	end
	begin
	#10;
	$display ($time, " %s, Process:3", name);
	end
	join_any
	disable LABLE;
	$display ($time, " %s, multiple_process completed", name);
	endtask : multiple_process
	endclass : abc
	module top2();
	abc a1;
	initial begin
	a1 = new();
	a1.name = "a1";
	a1.multiple_process(5);
	#30 $finish;
	end
	endmodule : top2
	//Output:
	// 5 a1, Process:2
	// 5 a1, multiple_process completed
	// 20 a1, Process:1

view raw disable_process_2.sv hosted with ❤ by GitHub

------------------------------------------------------------------------------

Above code works fine with a single instance of that class. But when there are multiple instances of the same class in the test-bench and all the instances are executing their threads simultaneously then the simulation will stop after executing "disable LABEL" statement of any instance.
------------------------------------------------------------------------------

	class abc;
	string name;
	task multiple_process(input int unsigned delay);
	fork
	begin
	forever begin
	#20;
	$display ($time, " %s, Process:1", name);
	end
	end
	join_none
	fork : LABLE
	begin
	#delay;
	$display ($time, " %s, Process:2", name);
	end
	begin
	#10;
	$display ($time, " %s, Process:3", name);
	end
	join_any
	disable LABLE;
	$display ($time, " %s, multiple_process completed", name);
	endtask : multiple_process
	endclass : abc
	module top2();
	abc a1, a2;
	initial begin
	a1 = new();
	a1.name = "a1";
	a2 = new();
	a2.name = "a2";
	fork
	a1.multiple_process(5);
	a2.multiple_process(7);
	join
	#30 $finish;
	end
	endmodule : top2
	//Output:
	// 5 a1, Process:2
	// 5 a1, multiple_process completed
	// 5 a2, multiple_process completed
	// 20 a1, Process:1
	// 20 a2, Process:1

view raw disable_process_3.sv hosted with ❤ by GitHub

------------------------------------------------------------------------------

There are two ways to handle these kind of situations.
1) Limiting scope of "disable fork" by adding one extra hierarchy of fork...join.
2) Using "process" class of SystemVerilog

Let's see both ways through example,
------------------------------------------------------------------------------

	class abc;
	string name;
	task multiple_process(input int unsigned delay);
	fork
	begin
	forever begin
	#20;
	$display ($time, " %s, Process:1", name);
	end
	end
	join_none
	fork
	begin
	fork //extra level of hierarchy to limit scope of "disable fork"
	begin
	#delay;
	$display ($time, " %s, Process:2", name);
	end
	begin
	#10;
	$display ($time, " %s, Process:3", name);
	end
	join_any
	disable fork;
	end
	join //extra level of hierarchy to limit scope of "disable fork"
	$display ($time, " %s, multiple_process completed", name);
	endtask : multiple_process
	endclass : abc
	module top3();
	abc a1, a2;
	initial begin
	a1 = new();
	a1.name = "a1";
	a2 = new();
	a2.name = "a2";
	fork
	a1.multiple_process(5);
	a2.multiple_process(7);
	join
	#30 $finish;
	end
	endmodule : top3
	//Output:
	// 5 a1, Process:2
	// 5 a1, multiple_process completed
	// 7 a2, Process:2
	// 7 a2, multiple_process completed
	// 20 a1, Process:1
	// 20 a2, Process:1

view raw disable_process_4.sv hosted with ❤ by GitHub

------------------------------------------------------------------------------


------------------------------------------------------------------------------

	class abc;
	string name;
	process process2;
	process process3;
	task multiple_process(input int unsigned delay);
	fork
	begin
	forever begin
	#20;
	$display ($time, " %s, Process:1", name);
	end
	end
	join_none
	fork
	begin
	process2 = process::self();
	#delay;
	$display ($time, " %s, Process:2", name);
	end
	begin
	process3 = process::self();
	#10;
	$display ($time, " %s, Process:3", name);
	end
	join_any
	if (process2.status != process::FINISHED) begin
	process2.kill();
	end
	if (process3.status != process::FINISHED) begin
	process3.kill();
	end
	$display ($time, " %s, multiple_process completed", name);
	endtask : multiple_process
	endclass : abc
	module top3();
	abc a1, a2;
	initial begin
	a1 = new();
	a1.name = "a1";
	a2 = new();
	a2.name = "a2";
	fork
	a1.multiple_process(5);
	a2.multiple_process(7);
	join
	#30 $finish;
	end
	endmodule : top3
	//Output:
	// 5 a1, Process:2
	// 5 a1, multiple_process completed
	// 7 a2, Process:2
	// 7 a2, multiple_process completed
	// 20 a1, Process:1
	// 20 a2, Process:1

view raw disable_process_5.sv hosted with ❤ by GitHub

------------------------------------------------------------------------------

Wait for more than one processes of fork...join_none to complete

In our project some time we want to wait for more than one process which is invoked from fork...join_none or join_any before proceeding further.

How to achieve this using SystemVerilog constructs, that we will understand through an example.

Let's go through below code,
-------------------------------------------------------------------------------------

	class abc;
	semaphore s;
	function new();
	s = new(0); // Initialized with zero key
	endfunction : new
	task multiple_process();
	fork
	begin : process1
	#5;
	$display ($time," process1");
	s.put(1);
	end
	begin
	#10;
	$display ($time," process2");
	s.put(1);
	end
	begin
	#15;
	$display ($time," process3");
	s.put(1);
	end
	begin
	#12;
	$display ($time," process4");
	s.put(1);
	end
	join_none // You can use join_any also
	s.get(2); // wait for any two process to be completed
	disable fork; // kills remaining process
	s = null; // removes semaphore (if you plan to reuse s)
	$display ($time," multiple_process completed");
	endtask : multiple_process
	endclass : abc
	module top();
	abc A;
	initial begin
	A = new();
	A.multiple_process();
	end
	endmodule : top
	//Output:
	// 5 process1
	// 10 process2
	// 10 multiple_process completed

view raw wait_for_more_than_1_process_using_fork_join.sv hosted with ❤ by GitHub

-------------------------------------------------------------------------------------

In above code, class abc is having one method named multiple_process().
In API, within fork...join_none 4 process are invoked in parallel.
Each process puts one key into semaphore just before it's completed (Initially semaphore doesn't have any key).

After fork...join_none, I am waiting for semaphore to get at least two key ().

Callback vs Factory in UVM

Callbacks and factory address different areas of re-usability.

Callback: Add functionality to existing logic.

Factory: Change the existing component before build, keeps environment same.

Although the callback and factory can be interchangeably used to address the same problem. Depending on the need and demand, a wise decision should be made while adopting either of the techniques as they have their own merits and demerits.

Strength in Verilog

Strengths can be used to resolve which value should appear on a net or gate output.
A strength specification shall have the following two components:
• The strength of the 0 portion of the net value, called strength0, designated as one of the following:
supply0 strong0 pull0 weak0 highz0
• The strength of the 1 portion of the net value, called strength1, designated as one of the following:
supply1 strong1 pull1 weak1 highz1
The combinations (highz0, highz1) and (highz1, highz0) shall be considered illegal.

There are four driving strengths: supply strong pull weak
Signals with driving strengths shall propagate from gate outputs and continuous assignment outputs.

There are three charge storage strengths: large medium small
Signals with the charge storage strengths shall originate in the trireg net type.

It is possible to think of the strengths of signals as locations on the scale

When signals combine, their strengths and values shall determine the strength and value of the resulting signal in accordance with the principle.

1) If two or more drivers drive a signal with different strength then it will have the value of the strongest driver
Ex-1:
buf (strong1, weak0) g1 (y, a);
buf (pull1, supply0) g2 (y, b);
• If a = 0 and b = 0 then y will be 0 with supply strength because both gates will set y to 0 and supply (7) strength has bigger value than weak (3) strength.
• If a = 0 and b = 1 then y will be 1 with pull strength because g1 will set y to 0 with weak (3) strength and g2 will set y to 1 with pull (5) strength (pull strength is stronger than the weak strength).
• If a = 1 and b = 0 then y will be 0 with supply strength because g1 will set y to 1 with strong (6) strength and g2 will set y to 0 with supply (7) strength (supply strength is stronger than the strong strength).
• If a = 1 and b = 1 then y will be 1 with strong strength because g1 will set y to 1 with strong (6) strength and g2 will set y to 1 with pull (5) strength.

2) The combination of signals identical in strength and value shall result in the same signal (If two drivers of a net have the same strength and value, then the net result will have the same value and strength)
Ex-2:
buf (strong1, weak0) g1 (y, a);
buf (strong1, weak0) g1 (y, b);
• If a = 0 and b = 0 then y will be 0 with weak strength.
• If a = 1 and b = 1 then y will be 1 with strong strength.

3) If two drivers of a net have the same strength but different values then signal value will be unknown and it will have the same strength as both drivers
Ex-3:
buf (strong1, weak0) g1 (y, a);
buf (weak1, strong0) g1 (y, b);
• If a = 1 and b = 0 then y will be x with strong strength.

Important Notes:
If one of the drivers has an H or L value, then the output value will be X.

Reference:
1) http://verilog.renerta.com/source/vrg00047.htm
2) System Verilog LRM (1800-2012)

Override in UVM using factory with Example

One of the main advantage of UVM is Creating each components using factory enables them to be overridden in different tests or environments without changing underlying code base.

uvm_factory provides four different methods to override particular instance or all instances of particular class.
set_inst_override_by_type
set_inst_override_by_name
set_type_override_by_type
set_type_override_by_name

Let's go through example of each one of above four ways.

set_inst_override_by_type
-------------------------------------------------------

	// set_inst_override_by_type
	`include "uvm.svh"
	import uvm_pkg::*;
	//--------------------uvm_component------------------------------
	class A extends uvm_agent;
	`uvm_component_utils(A)
	function new (string name="A", uvm_component parent);
	super.new(name, parent);
	`uvm_info(get_full_name, $sformatf("A new"), UVM_LOW);
	endfunction : new
	virtual function hello();
	`uvm_info(get_full_name, $sformatf("HELLO from Original class 'A'"), UVM_LOW);
	endfunction : hello
	endclass : A
	class A_ovr extends A;
	`uvm_component_utils(A_ovr)
	function new (string name="A_ovr", uvm_component parent);
	super.new(name, parent);
	`uvm_info(get_full_name, $sformatf("A_ovr new"), UVM_LOW);
	endfunction : new
	function hello();
	`uvm_info(get_full_name, $sformatf("HELLO from override class 'A_ovr'"), UVM_LOW);
	endfunction : hello
	endclass : A_ovr
	//--------------------uvm_object------------------------------
	class B extends uvm_object;
	`uvm_object_utils(B)
	function new (string name="B");
	super.new(name);
	`uvm_info(get_full_name, $sformatf("B new"), UVM_LOW);
	endfunction : new
	virtual function hello();
	`uvm_info(get_full_name, $sformatf("HELLO from Original class 'B'"), UVM_LOW);
	endfunction : hello
	endclass : B
	class B_ovr extends B;
	`uvm_object_utils(B_ovr)
	function new (string name="B_ovr");
	super.new(name);
	`uvm_info(get_full_name, $sformatf("B_ovr new"), UVM_LOW);
	endfunction : new
	function hello();
	`uvm_info(get_full_name, $sformatf("HELLO from override class 'B_ovr'"), UVM_LOW);
	endfunction : hello
	endclass : B_ovr
	class B_override extends B_ovr;
	`uvm_object_utils(B_override)
	function new (string name="B_override");
	super.new(name);
	`uvm_info(get_full_name, $sformatf("B_override new"), UVM_LOW);
	endfunction : new
	function hello();
	`uvm_info(get_full_name, $sformatf("HELLO from override class 'B_override'"), UVM_LOW);
	endfunction : hello
	endclass : B_override
	//--------------------env class--------------------
	class environment extends uvm_env;
	`uvm_component_utils(environment)
	A a1;
	B b1, b2;
	function new(string name="environment", uvm_component parent);
	super.new(name, parent);
	endfunction : new
	function void build_phase(uvm_phase phase);
	super.build_phase(phase);
	// arguments of create method:
	// 1. string name = ""
	// 2. uvm_component parent = null
	// 3. string contxt = ""
	// The contxt argument, if supplied, supercedes the parent's context.
	a1 = A::type_id::create("a1", this);
	b1 = B::type_id::create("b1", , "path1");
	b2 = B::type_id::create("b2", , "path2");
	a1.hello(); // This will print from overridden class A_ovr
	b1.hello(); // This will print from overridden class B_ovr
	b2.hello(); // This will print from overridden class B_override
	endfunction : build_phase
	endclass : environment
	//-------------------test class--------------------------
	class test extends uvm_test;
	`uvm_component_utils(test)
	environment env;
	function new(string name = "test", uvm_component parent = null);
	super.new(name, parent);
	endfunction : new
	virtual function void build_phase(uvm_phase phase);
	super.build_phase(phase);
	env = environment::type_id::create("env", this);
	`uvm_info(get_full_name, $sformatf("TEST set_inst_override_by_type"), UVM_LOW);
	factory.set_inst_override_by_type(A::get_type(), A_ovr::get_type(), {get_full_name, ".", "env.a1"}); // Working
	//factory.set_inst_override_by_type(B::get_type(), B_ovr::get_type(), {get_full_name, ".", "env.b1"}); // Not working
	factory.set_inst_override_by_type(B::get_type(), B_ovr::get_type(), "path1.b1"); // Working
	//factory.set_inst_override_by_type(B::get_type(), B_override::get_type(), {get_full_name, ".", "env.b2"}); // Not working
	factory.set_inst_override_by_type(B::get_type(), B_override::get_type(), "path2.b2"); // Working
	factory.print(); // This will print info about overridden classes.
	endfunction : build_phase
	endclass : test
	module top();
	initial begin
	run_test("test");
	end
	endmodule : top

view raw set_instance_override_by_type.sv hosted with ❤ by GitHub

-------------------------------------------------------

-------------------------------------------------------

	//Output:
	// UVM_INFO @ 0: reporter [RNTST] Running test test...
	// UVM_INFO top.sv(118) @ 0: uvm_test_top [uvm_test_top] TEST set_inst_override_by_type
	//
	// #### Factory Configuration (*)
	// Instance Overrides:
	// Requested Type Override Path Override Type
	// -------------- ------------------- -------------
	// A uvm_test_top.env.a1 A_ovr
	// B path1.b1 B_ovr
	// B path2.b2 B_override
	//
	// No type overrides are registered with this factory
	//
	// All types registered with the factory: 45 total
	// (types without type names will not be printed)
	// Type Name
	// ---------
	// A
	// A_ovr
	// B
	// B_override
	// B_ovr
	// environment
	// test
	// (*) Types with no associated type name will be printed as <unknown>
	// ####
	//
	// UVM_INFO top.sv(15) @ 0: uvm_test_top.env.a1 [uvm_test_top.env.a1] A new
	// UVM_INFO top.sv(28) @ 0: uvm_test_top.env.a1 [uvm_test_top.env.a1] A_ovr new
	// UVM_INFO top.sv(42) @ 0: reporter [B_ovr] B new
	// UVM_INFO top.sv(55) @ 0: reporter [B_ovr] B_ovr new
	// UVM_INFO top.sv(42) @ 0: reporter [B_override] B new
	// UVM_INFO top.sv(55) @ 0: reporter [B_override] B_ovr new
	// UVM_INFO top.sv(68) @ 0: reporter [B_override] B_override new
	// UVM_INFO top.sv(32) @ 0: uvm_test_top.env.a1 [uvm_test_top.env.a1] HELLO from override class 'A_ovr'
	// UVM_INFO top.sv(59) @ 0: reporter [b1] HELLO from override class 'B_ovr'
	// UVM_INFO top.sv(72) @ 0: reporter [b2] HELLO from override class 'B_override'

view raw set_instance_override_by_type_op.sv hosted with ❤ by GitHub

-------------------------------------------------------


set_inst_override_by_name
-------------------------------------------------------

	// set_inst_override_by_name
	`include "uvm.svh"
	import uvm_pkg::*;
	//--------------------uvm_component------------------------------
	class A extends uvm_agent;
	`uvm_component_utils(A)
	function new (string name="A", uvm_component parent);
	super.new(name, parent);
	`uvm_info(get_full_name, $sformatf("A new"), UVM_LOW);
	endfunction : new
	virtual function hello();
	`uvm_info(get_full_name, $sformatf("HELLO from Original class 'A'"), UVM_LOW);
	endfunction : hello
	endclass : A
	class A_ovr extends A;
	`uvm_component_utils(A_ovr)
	function new (string name="A_ovr", uvm_component parent);
	super.new(name, parent);
	`uvm_info(get_full_name, $sformatf("A_ovr new"), UVM_LOW);
	endfunction : new
	function hello();
	`uvm_info(get_full_name, $sformatf("HELLO from override class 'A_ovr'"), UVM_LOW);
	endfunction : hello
	endclass : A_ovr
	//--------------------uvm_object------------------------------
	class B extends uvm_object;
	`uvm_object_utils(B)
	function new (string name="B");
	super.new(name);
	`uvm_info(get_full_name, $sformatf("B new"), UVM_LOW);
	endfunction : new
	virtual function hello();
	`uvm_info(get_full_name, $sformatf("HELLO from Original class 'B'"), UVM_LOW);
	endfunction : hello
	endclass : B
	class B_ovr extends B;
	`uvm_object_utils(B_ovr)
	function new (string name="B_ovr");
	super.new(name);
	`uvm_info(get_full_name, $sformatf("B_ovr new"), UVM_LOW);
	endfunction : new
	function hello();
	`uvm_info(get_full_name, $sformatf("HELLO from override class 'B_ovr'"), UVM_LOW);
	endfunction : hello
	endclass : B_ovr
	class B_override extends B_ovr;
	`uvm_object_utils(B_override)
	function new (string name="B_override");
	super.new(name);
	`uvm_info(get_full_name, $sformatf("B_override new"), UVM_LOW);
	endfunction : new
	function hello();
	`uvm_info(get_full_name, $sformatf("HELLO from override class 'B_override'"), UVM_LOW);
	endfunction : hello
	endclass : B_override
	//--------------------env class--------------------
	class environment extends uvm_env;
	`uvm_component_utils(environment)
	A a1;
	B b1, b2;
	function new(string name="environment", uvm_component parent);
	super.new(name, parent);
	endfunction : new
	function void build_phase(uvm_phase phase);
	super.build_phase(phase);
	// arguments of create method:
	// 1. string name = ""
	// 2. uvm_component parent = null
	// 3. string contxt = ""
	// The contxt argument, if supplied, supercedes the parent's context.
	a1 = A::type_id::create("a1", this);
	b1 = B::type_id::create("b1", , "path1");
	b2 = B::type_id::create("b2", , "path2");
	a1.hello(); // This will print from overridden class A_ovr
	b1.hello(); // This will print from overridden class B_ovr
	b2.hello(); // This will print from overridden class B_override
	endfunction : build_phase
	endclass : environment
	//-------------------test class--------------------------
	class test extends uvm_test;
	`uvm_component_utils(test)
	environment env;
	function new(string name = "test", uvm_component parent = null);
	super.new(name, parent);
	endfunction : new
	virtual function void build_phase(uvm_phase phase);
	super.build_phase(phase);
	env = environment::type_id::create("env", this);
	`uvm_info(get_full_name, $sformatf("TEST set_inst_override_by_name"), UVM_LOW);
	factory.set_inst_override_by_name("A", "A_ovr", {get_full_name, ".", "env.a1"}); // Working
	//factory.set_inst_override_by_name("B", "B_ovr", {get_full_name, ".", "env.b1"}); // Not working
	factory.set_inst_override_by_name("B", "B_ovr", "path1.b1"); // Working
	//factory.set_inst_override_by_name("B", "B_override", {get_full_name, ".", "env.b2"}); // Not working
	factory.set_inst_override_by_name("B", "B_override", "path2.b2"); // Working
	factory.print(); // This will print info about overridden classes.
	endfunction : build_phase
	endclass : test
	module top();
	initial begin
	run_test("test");
	end
	endmodule : top

view raw set_instance_override_by_name.sv hosted with ❤ by GitHub

-------------------------------------------------------

-------------------------------------------------------

	//Output:
	// UVM_INFO @ 0: reporter [RNTST] Running test test...
	// UVM_INFO top.sv(118) @ 0: uvm_test_top [uvm_test_top] TEST set_inst_override_by_name
	//
	// #### Factory Configuration (*)
	// Instance Overrides:
	// Requested Type Override Path Override Type
	// -------------- ------------------- -------------
	// A uvm_test_top.env.a1 A_ovr
	// B path1.b1 B_ovr
	// B path2.b2 B_override
	//
	// No type overrides are registered with this factory
	//
	// All types registered with the factory: 45 total
	// (types without type names will not be printed)
	// Type Name
	// ---------
	// A
	// A_ovr
	// B
	// B_override
	// B_ovr
	// environment
	// test
	// (*) Types with no associated type name will be printed as <unknown>
	// ####
	//
	// UVM_INFO top.sv(15) @ 0: uvm_test_top.env.a1 [uvm_test_top.env.a1] A new
	// UVM_INFO top.sv(28) @ 0: uvm_test_top.env.a1 [uvm_test_top.env.a1] A_ovr new
	// UVM_INFO top.sv(42) @ 0: reporter [B_ovr] B new
	// UVM_INFO top.sv(55) @ 0: reporter [B_ovr] B_ovr new
	// UVM_INFO top.sv(42) @ 0: reporter [B_override] B new
	// UVM_INFO top.sv(55) @ 0: reporter [B_override] B_ovr new
	// UVM_INFO top.sv(68) @ 0: reporter [B_override] B_override new
	// UVM_INFO top.sv(32) @ 0: uvm_test_top.env.a1 [uvm_test_top.env.a1] HELLO from override class 'A_ovr'
	// UVM_INFO top.sv(59) @ 0: reporter [b1] HELLO from override class 'B_ovr'
	// UVM_INFO top.sv(72) @ 0: reporter [b2] HELLO from override class 'B_override'

view raw set_instance_override_by_name_op.sv hosted with ❤ by GitHub

-------------------------------------------------------


set_type_override_by_type
-------------------------------------------------------

	// set_type_override_by_type
	`include "uvm.svh"
	import uvm_pkg::*;
	//--------------------uvm_component------------------------------
	class A extends uvm_agent;
	`uvm_component_utils(A)
	function new (string name="A", uvm_component parent);
	super.new(name, parent);
	`uvm_info(get_full_name, $sformatf("A new"), UVM_LOW);
	endfunction : new
	virtual function void hello();
	`uvm_info(get_full_name, $sformatf("HELLO from Original class 'A'"), UVM_LOW);
	endfunction : hello
	endclass : A
	class A_ovr extends A;
	`uvm_component_utils(A_ovr)
	function new (string name="A_ovr", uvm_component parent);
	super.new(name, parent);
	`uvm_info(get_full_name, $sformatf("A_ovr new"), UVM_LOW);
	endfunction : new
	function void hello();
	`uvm_info(get_full_name, $sformatf("HELLO from override class 'A_ovr'"), UVM_LOW);
	endfunction : hello
	endclass : A_ovr
	//--------------------uvm_object------------------------------
	class B extends uvm_object;
	`uvm_object_utils(B)
	function new (string name="B");
	super.new(name);
	`uvm_info(get_full_name, $sformatf("B new"), UVM_LOW);
	endfunction : new
	virtual function void hello();
	`uvm_info(get_full_name, $sformatf("HELLO from Original class 'B'"), UVM_LOW);
	endfunction : hello
	endclass : B
	class B_ovr extends B;
	`uvm_object_utils(B_ovr)
	function new (string name="B_ovr");
	super.new(name);
	`uvm_info(get_full_name, $sformatf("B_ovr new"), UVM_LOW);
	endfunction : new
	function void hello();
	`uvm_info(get_full_name, $sformatf("HELLO from override class 'B_ovr'"), UVM_LOW);
	endfunction : hello
	endclass : B_ovr
	class B_override extends B_ovr;
	`uvm_object_utils(B_override)
	function new (string name="B_override");
	super.new(name);
	`uvm_info(get_full_name, $sformatf("B_override new"), UVM_LOW);
	endfunction : new
	function void hello();
	`uvm_info(get_full_name, $sformatf("HELLO from override class 'B_override'"), UVM_LOW);
	endfunction : hello
	endclass : B_override
	//--------------------env class--------------------
	class environment extends uvm_env;
	`uvm_component_utils(environment)
	A a1;
	B b1, b2;
	function new(string name="environment", uvm_component parent);
	super.new(name, parent);
	endfunction : new
	function void build_phase(uvm_phase phase);
	super.build_phase(phase);
	// arguments of create method:
	// 1. string name = ""
	// 2. uvm_component parent = null
	// 3. string contxt = ""
	// The contxt argument, if supplied, supercedes the parent's context.
	a1 = A::type_id::create("a1", this);
	b1 = B::type_id::create("b1", , "path1");
	b2 = B::type_id::create("b2", , "path2");
	void'(a1.hello()); // This will print from overridden class A_ovr
	void'(b1.hello()); // This will print from overridden class B_override
	void'(b2.hello()); // This will print from overridden class B_override
	endfunction : build_phase
	endclass : environment
	//-------------------test class--------------------------
	class test extends uvm_test;
	`uvm_component_utils(test)
	environment env;
	function new(string name = "test", uvm_component parent = null);
	super.new(name, parent);
	endfunction : new
	virtual function void build_phase(uvm_phase phase);
	super.build_phase(phase);
	env = environment::type_id::create("env", this);
	`uvm_info(get_full_name, $sformatf("TEST set_inst_override_by_name"), UVM_LOW);
	factory.set_type_override_by_type(A::get_type(), A_ovr::get_type()); // Working
	factory.set_type_override_by_type(B::get_type(), B_override::get_type()); // Working
	factory.print(); // This will print info about overridden classes.
	endfunction : build_phase
	endclass : test
	module top();
	initial begin
	run_test("test");
	end
	endmodule : top

view raw set_type_override_by_type.sv hosted with ❤ by GitHub

-------------------------------------------------------

-------------------------------------------------------

	//Output:
	UVM_INFO @ 0: reporter [RNTST] Running test test...
	UVM_INFO testbench.sv(109) @ 0: uvm_test_top [uvm_test_top] TEST set_inst_override_by_name
	#### Factory Configuration (*)
	No instance overrides are registered with this factory
	Type Overrides:
	Requested Type Override Type
	-------------- -------------
	A A_ovr
	B B_override
	All types registered with the factory: 45 total
	(types without type names will not be printed)
	Type Name
	---------
	A
	A_ovr
	B
	B_override
	B_ovr
	environment
	snps_uvm_reg_bank_group
	snps_uvm_reg_map
	test
	(*) Types with no associated type name will be printed as <unknown>
	####
	UVM_INFO testbench.sv(9) @ 0: uvm_test_top.env.a1 [uvm_test_top.env.a1] A new
	UVM_INFO testbench.sv(22) @ 0: uvm_test_top.env.a1 [uvm_test_top.env.a1] A_ovr new
	UVM_INFO testbench.sv(36) @ 0: reporter [B_override] B new
	UVM_INFO testbench.sv(49) @ 0: reporter [B_override] B_ovr new
	UVM_INFO testbench.sv(62) @ 0: reporter [B_override] B_override new
	UVM_INFO testbench.sv(36) @ 0: reporter [B_override] B new
	UVM_INFO testbench.sv(49) @ 0: reporter [B_override] B_ovr new
	UVM_INFO testbench.sv(62) @ 0: reporter [B_override] B_override new
	UVM_INFO testbench.sv(26) @ 0: uvm_test_top.env.a1 [uvm_test_top.env.a1] HELLO from override class 'A_ovr'
	UVM_INFO testbench.sv(66) @ 0: reporter [b1] HELLO from override class 'B_override'
	UVM_INFO testbench.sv(66) @ 0: reporter [b2] HELLO from override class 'B_override'

view raw set_type_override_by_type_op.sv hosted with ❤ by GitHub

-------------------------------------------------------


set_type_override_by_name
-------------------------------------------------------

	// set_type_override_by_name
	`include "uvm.svh"
	import uvm_pkg::*;
	//--------------------uvm_component------------------------------
	class A extends uvm_agent;
	`uvm_component_utils(A)
	function new (string name="A", uvm_component parent);
	super.new(name, parent);
	`uvm_info(get_full_name, $sformatf("A new"), UVM_LOW);
	endfunction : new
	virtual function void hello();
	`uvm_info(get_full_name, $sformatf("HELLO from Original class 'A'"), UVM_LOW);
	endfunction : hello
	endclass : A
	class A_ovr extends A;
	`uvm_component_utils(A_ovr)
	function new (string name="A_ovr", uvm_component parent);
	super.new(name, parent);
	`uvm_info(get_full_name, $sformatf("A_ovr new"), UVM_LOW);
	endfunction : new
	function void hello();
	`uvm_info(get_full_name, $sformatf("HELLO from override class 'A_ovr'"), UVM_LOW);
	endfunction : hello
	endclass : A_ovr
	//--------------------uvm_object------------------------------
	class B extends uvm_object;
	`uvm_object_utils(B)
	function new (string name="B");
	super.new(name);
	`uvm_info(get_full_name, $sformatf("B new"), UVM_LOW);
	endfunction : new
	virtual function void hello();
	`uvm_info(get_full_name, $sformatf("HELLO from Original class 'B'"), UVM_LOW);
	endfunction : hello
	endclass : B
	class B_ovr extends B;
	`uvm_object_utils(B_ovr)
	function new (string name="B_ovr");
	super.new(name);
	`uvm_info(get_full_name, $sformatf("B_ovr new"), UVM_LOW);
	endfunction : new
	function void hello();
	`uvm_info(get_full_name, $sformatf("HELLO from override class 'B_ovr'"), UVM_LOW);
	endfunction : hello
	endclass : B_ovr
	class B_override extends B_ovr;
	`uvm_object_utils(B_override)
	function new (string name="B_override");
	super.new(name);
	`uvm_info(get_full_name, $sformatf("B_override new"), UVM_LOW);
	endfunction : new
	function void hello();
	`uvm_info(get_full_name, $sformatf("HELLO from override class 'B_override'"), UVM_LOW);
	endfunction : hello
	endclass : B_override
	//--------------------env class--------------------
	class environment extends uvm_env;
	`uvm_component_utils(environment)
	A a1;
	B b1, b2;
	B_ovr b3;
	function new(string name="environment", uvm_component parent);
	super.new(name, parent);
	endfunction : new
	function void build_phase(uvm_phase phase);
	super.build_phase(phase);
	// arguments of create method:
	// 1. string name = ""
	// 2. uvm_component parent = null
	// 3. string contxt = ""
	// The contxt argument, if supplied, supercedes the parent's context.
	// contxt argument is not required for set_type_override_*,
	// It is only required for set_inst_override_* to locate
	// instance of uvm_object which is not part of uvm hierarchy.
	a1 = A::type_id::create("a1", this);
	b1 = B::type_id::create("b1", , "path1");
	b2 = B::type_id::create("b2");
	b3 = B_ovr::type_id::create("b3");
	void'(a1.hello()); // This will print from overridden class A_ovr
	void'(b1.hello()); // This will print from overridden class B_override
	void'(b2.hello()); // This will print from overridden class B_override
	void'(b3.hello()); // This will print from overridden class B_ovr
	endfunction : build_phase
	endclass : environment
	//-------------------test class--------------------------
	class test extends uvm_test;
	`uvm_component_utils(test)
	environment env;
	function new(string name = "test", uvm_component parent = null);
	super.new(name, parent);
	endfunction : new
	virtual function void build_phase(uvm_phase phase);
	super.build_phase(phase);
	env = environment::type_id::create("env", this);
	`uvm_info(get_full_name, $sformatf("TEST set_inst_override_by_name"), UVM_LOW);
	factory.set_type_override_by_name("A", "A_ovr"); // Working
	factory.set_type_override_by_name("B", "B_override"); // Working
	factory.print(); // This will print info about overridden classes.
	endfunction : build_phase
	endclass : test
	module top();
	initial begin
	run_test("test");
	end
	endmodule : top

view raw set_type_override_by_name.sv hosted with ❤ by GitHub

-------------------------------------------------------

-------------------------------------------------------

	//Output:
	UVM_INFO @ 0: reporter [RNTST] Running test test...
	UVM_INFO testbench.sv(117) @ 0: uvm_test_top [uvm_test_top] TEST set_inst_override_by_name
	#### Factory Configuration (*)
	No instance overrides are registered with this factory
	Type Overrides:
	Requested Type Override Type
	-------------- -------------
	A A_ovr
	B B_override
	All types registered with the factory: 45 total
	(types without type names will not be printed)
	Type Name
	---------
	A
	A_ovr
	B
	B_override
	B_ovr
	environment
	snps_uvm_reg_bank_group
	snps_uvm_reg_map
	test
	(*) Types with no associated type name will be printed as <unknown>
	####
	UVM_INFO testbench.sv(11) @ 0: uvm_test_top.env.a1 [uvm_test_top.env.a1] A new
	UVM_INFO testbench.sv(24) @ 0: uvm_test_top.env.a1 [uvm_test_top.env.a1] A_ovr new
	UVM_INFO testbench.sv(38) @ 0: reporter [B_override] B new
	UVM_INFO testbench.sv(51) @ 0: reporter [B_override] B_ovr new
	UVM_INFO testbench.sv(64) @ 0: reporter [B_override] B_override new
	UVM_INFO testbench.sv(38) @ 0: reporter [B_override] B new
	UVM_INFO testbench.sv(51) @ 0: reporter [B_override] B_ovr new
	UVM_INFO testbench.sv(64) @ 0: reporter [B_override] B_override new
	UVM_INFO testbench.sv(38) @ 0: reporter [B_ovr] B new
	UVM_INFO testbench.sv(51) @ 0: reporter [B_ovr] B_ovr new
	UVM_INFO testbench.sv(28) @ 0: uvm_test_top.env.a1 [uvm_test_top.env.a1] HELLO from override class 'A_ovr'
	UVM_INFO testbench.sv(68) @ 0: reporter [b1] HELLO from override class 'B_override'
	UVM_INFO testbench.sv(68) @ 0: reporter [b2] HELLO from override class 'B_override'
	UVM_INFO testbench.sv(55) @ 0: reporter [b3] HELLO from override class 'B_ovr'

view raw set_type_override_by_name_op.sv hosted with ❤ by GitHub

-------------------------------------------------------

set_inst_override_* has high precedence than set_type_override_*.
i.e. If any particular instance of class is override by using set_inst_override_* and type of same class is overridden by using set_type_override_* then that particular instance of class is overridden by set_inst_override_* and rest other instances are overridden by set_type_override_*

-------------------------------------------------------

	// set_inst_override_* hase high priority than set_type_override_*
	`include "uvm.svh"
	import uvm_pkg::*;
	//--------------------uvm_component------------------------------
	class A extends uvm_agent;
	`uvm_component_utils(A)
	function new (string name="A", uvm_component parent);
	super.new(name, parent);
	`uvm_info(get_full_name, $sformatf("A new"), UVM_LOW);
	endfunction : new
	virtual function void hello();
	`uvm_info(get_full_name, $sformatf("HELLO from Original class 'A'"), UVM_LOW);
	endfunction : hello
	endclass : A
	class A_ovr extends A;
	`uvm_component_utils(A_ovr)
	function new (string name="A_ovr", uvm_component parent);
	super.new(name, parent);
	`uvm_info(get_full_name, $sformatf("A_ovr new"), UVM_LOW);
	endfunction : new
	function void hello();
	`uvm_info(get_full_name, $sformatf("HELLO from override class 'A_ovr'"), UVM_LOW);
	endfunction : hello
	endclass : A_ovr
	class A_override extends A;
	`uvm_component_utils(A_override)
	function new (string name="A_override", uvm_component parent);
	super.new(name, parent);
	`uvm_info(get_full_name, $sformatf("A_override new"), UVM_LOW);
	endfunction : new
	function void hello();
	`uvm_info(get_full_name, $sformatf("HELLO from override class 'A_override'"), UVM_LOW);
	endfunction : hello
	endclass : A_override
	//--------------------uvm_object------------------------------
	class B extends uvm_object;
	`uvm_object_utils(B)
	function new (string name="B");
	super.new(name);
	`uvm_info(get_full_name, $sformatf("B new"), UVM_LOW);
	endfunction : new
	virtual function void hello();
	`uvm_info(get_full_name, $sformatf("HELLO from Original class 'B'"), UVM_LOW);
	endfunction : hello
	endclass : B
	class B_ovr extends B;
	`uvm_object_utils(B_ovr)
	function new (string name="B_ovr");
	super.new(name);
	`uvm_info(get_full_name, $sformatf("B_ovr new"), UVM_LOW);
	endfunction : new
	function void hello();
	`uvm_info(get_full_name, $sformatf("HELLO from override class 'B_ovr'"), UVM_LOW);
	endfunction : hello
	endclass : B_ovr
	class B_override extends B_ovr;
	`uvm_object_utils(B_override)
	function new (string name="B_override");
	super.new(name);
	`uvm_info(get_full_name, $sformatf("B_override new"), UVM_LOW);
	endfunction : new
	function void hello();
	`uvm_info(get_full_name, $sformatf("HELLO from override class 'B_override'"), UVM_LOW);
	endfunction : hello
	endclass : B_override
	//--------------------env class--------------------
	class environment extends uvm_env;
	`uvm_component_utils(environment)
	A a1, a2, a3;
	B b1, b2, b3;
	function new(string name="environment", uvm_component parent);
	super.new(name, parent);
	endfunction : new
	function void build_phase(uvm_phase phase);
	super.build_phase(phase);
	a1 = A::type_id::create("a1", this);
	a2 = A::type_id::create("a2", this);
	a3 = A::type_id::create("a3", this);
	b1 = B::type_id::create("b1", , "path1");
	b2 = B::type_id::create("b2", , "path2");
	b3 = B::type_id::create("b3", , "path3");
	void'(a1.hello()); // This will print from overridden class A_ovr
	void'(a2.hello()); // This will print from overridden class A_ovr
	void'(a3.hello()); // This will print from overridden class A_override
	void'(b1.hello()); // This will print from overridden class B_ovr
	void'(b2.hello()); // This will print from overridden class B_override
	void'(b3.hello()); // This will print from overridden class B_override
	endfunction : build_phase
	endclass : environment
	//-------------------test class--------------------------
	class test extends uvm_test;
	`uvm_component_utils(test)
	environment env;
	function new(string name = "test", uvm_component parent = null);
	super.new(name, parent);
	endfunction : new
	virtual function void build_phase(uvm_phase phase);
	super.build_phase(phase);
	env = environment::type_id::create("env", this);
	`uvm_info(get_full_name, $sformatf("TEST set_inst_override_by_name"), UVM_LOW);
	factory.set_type_override_by_type(A::get_type(), A_ovr::get_type()); // Working
	factory.set_type_override_by_name("B", "B_override"); // Working
	factory.set_inst_override_by_type(A::get_type(), A_override::get_type(), {get_full_name, ".", "env.a3"});
	factory.set_inst_override_by_name("B", "B_ovr", "path1.b1");
	factory.print(); // This will print info about overridden classes.
	endfunction : build_phase
	endclass : test
	module top();
	initial begin
	run_test("test");
	end
	endmodule : top

view raw override_precedence.sv hosted with ❤ by GitHub

-------------------------------------------------------

-------------------------------------------------------

	//Output:
	UVM_INFO @ 0: reporter [RNTST] Running test test...
	UVM_INFO testbench.sv(122) @ 0: uvm_test_top [uvm_test_top] TEST set_inst_override_by_name
	#### Factory Configuration (*)
	Instance Overrides:
	Requested Type Override Path Override Type
	-------------- ------------------- -------------
	A uvm_test_top.env.a3 A_override
	B path1.b1 B_ovr
	Type Overrides:
	Requested Type Override Type
	-------------- -------------------
	A A_ovr
	B B_override
	All types registered with the factory: 46 total
	(types without type names will not be printed)
	Type Name
	---------
	A
	A_override
	A_ovr
	B
	B_override
	B_ovr
	environment
	snps_uvm_reg_bank_group
	snps_uvm_reg_map
	test
	(*) Types with no associated type name will be printed as <unknown>
	####
	UVM_INFO testbench.sv(7) @ 0: uvm_test_top.env.a1 [uvm_test_top.env.a1] A new
	UVM_INFO testbench.sv(20) @ 0: uvm_test_top.env.a1 [uvm_test_top.env.a1] A_ovr new
	UVM_INFO testbench.sv(7) @ 0: uvm_test_top.env.a2 [uvm_test_top.env.a2] A new
	UVM_INFO testbench.sv(20) @ 0: uvm_test_top.env.a2 [uvm_test_top.env.a2] A_ovr new
	UVM_INFO testbench.sv(7) @ 0: uvm_test_top.env.a3 [uvm_test_top.env.a3] A new
	UVM_INFO testbench.sv(33) @ 0: uvm_test_top.env.a3 [uvm_test_top.env.a3] A_override new
	UVM_INFO testbench.sv(47) @ 0: reporter [B_ovr] B new
	UVM_INFO testbench.sv(60) @ 0: reporter [B_ovr] B_ovr new
	UVM_INFO testbench.sv(47) @ 0: reporter [B_override] B new
	UVM_INFO testbench.sv(60) @ 0: reporter [B_override] B_ovr new
	UVM_INFO testbench.sv(73) @ 0: reporter [B_override] B_override new
	UVM_INFO testbench.sv(47) @ 0: reporter [B_override] B new
	UVM_INFO testbench.sv(60) @ 0: reporter [B_override] B_ovr new
	UVM_INFO testbench.sv(73) @ 0: reporter [B_override] B_override new
	UVM_INFO testbench.sv(24) @ 0: uvm_test_top.env.a1 [uvm_test_top.env.a1] HELLO from override class 'A_ovr'
	UVM_INFO testbench.sv(24) @ 0: uvm_test_top.env.a2 [uvm_test_top.env.a2] HELLO from override class 'A_ovr'
	UVM_INFO testbench.sv(37) @ 0: uvm_test_top.env.a3 [uvm_test_top.env.a3] HELLO from override class 'A_override'
	UVM_INFO testbench.sv(64) @ 0: reporter [b1] HELLO from override class 'B_ovr'
	UVM_INFO testbench.sv(77) @ 0: reporter [b2] HELLO from override class 'B_override'
	UVM_INFO testbench.sv(77) @ 0: reporter [b3] HELLO from override class 'B_override'

view raw override_precedence_op.sv hosted with ❤ by GitHub

-------------------------------------------------------



UVM also support override through command line,
+uvm_set_inst_override=,,
+uvm_set_type_override=,[,]
work like the name based overrides in the factory--factory.set_inst_override_by_name() and factory.set_type_override_by_name().

Let's implement same example as above using command line arguments.
-------------------------------------------------------

	//--------------------uvm_component------------------------------
	class A extends uvm_agent;
	`uvm_component_utils(A)
	function new (string name="A", uvm_component parent);
	super.new(name, parent);
	`uvm_info(get_full_name, $sformatf("A new"), UVM_LOW);
	endfunction : new
	virtual function void hello();
	`uvm_info(get_full_name, $sformatf("HELLO from Original class 'A'"), UVM_LOW);
	endfunction : hello
	endclass : A
	class A_ovr extends A;
	`uvm_component_utils(A_ovr)
	function new (string name="A_ovr", uvm_component parent);
	super.new(name, parent);
	`uvm_info(get_full_name, $sformatf("A_ovr new"), UVM_LOW);
	endfunction : new
	function void hello();
	`uvm_info(get_full_name, $sformatf("HELLO from override class 'A_ovr'"), UVM_LOW);
	endfunction : hello
	endclass : A_ovr
	class A_override extends A;
	`uvm_component_utils(A_override)
	function new (string name="A_override", uvm_component parent);
	super.new(name, parent);
	`uvm_info(get_full_name, $sformatf("A_override new"), UVM_LOW);
	endfunction : new
	function void hello();
	`uvm_info(get_full_name, $sformatf("HELLO from override class 'A_override'"), UVM_LOW);
	endfunction : hello
	endclass : A_override
	//--------------------uvm_object------------------------------
	class B extends uvm_object;
	`uvm_object_utils(B)
	function new (string name="B");
	super.new(name);
	`uvm_info(get_full_name, $sformatf("B new"), UVM_LOW);
	endfunction : new
	virtual function void hello();
	`uvm_info(get_full_name, $sformatf("HELLO from Original class 'B'"), UVM_LOW);
	endfunction : hello
	endclass : B
	class B_ovr extends B;
	`uvm_object_utils(B_ovr)
	function new (string name="B_ovr");
	super.new(name);
	`uvm_info(get_full_name, $sformatf("B_ovr new"), UVM_LOW);
	endfunction : new
	function void hello();
	`uvm_info(get_full_name, $sformatf("HELLO from override class 'B_ovr'"), UVM_LOW);
	endfunction : hello
	endclass : B_ovr
	class B_override extends B_ovr;
	`uvm_object_utils(B_override)
	function new (string name="B_override");
	super.new(name);
	`uvm_info(get_full_name, $sformatf("B_override new"), UVM_LOW);
	endfunction : new
	function void hello();
	`uvm_info(get_full_name, $sformatf("HELLO from override class 'B_override'"), UVM_LOW);
	endfunction : hello
	endclass : B_override
	//--------------------env class--------------------
	class environment extends uvm_env;
	`uvm_component_utils(environment)
	A a1, a2, a3;
	B b1, b2, b3;
	function new(string name="environment", uvm_component parent);
	super.new(name, parent);
	endfunction : new
	function void build_phase(uvm_phase phase);
	super.build_phase(phase);
	a1 = A::type_id::create("a1", this);
	a2 = A::type_id::create("a2", this);
	a3 = A::type_id::create("a3", this);
	b1 = B::type_id::create("b1", , "path1");
	b2 = B::type_id::create("b2", , "path2");
	b3 = B::type_id::create("b3", , "path3");
	void'(a1.hello()); // This will print from overridden class A_ovr
	void'(a2.hello()); // This will print from overridden class A_ovr
	void'(a3.hello()); // This will print from overridden class A_override
	void'(b1.hello()); // This will print from overridden class B_ovr
	void'(b2.hello()); // This will print from overridden class B_override
	void'(b3.hello()); // This will print from overridden class B_override
	endfunction : build_phase
	endclass : environment
	//-------------------test class--------------------------
	class test extends uvm_test;
	`uvm_component_utils(test)
	environment env;
	function new(string name = "test", uvm_component parent = null);
	super.new(name, parent);
	endfunction : new
	virtual function void build_phase(uvm_phase phase);
	super.build_phase(phase);
	env = environment::type_id::create("env", this);
	`uvm_info(get_full_name, $sformatf("TEST set_inst_override_by_name"), UVM_LOW);
	//factory.set_type_override_by_type(A::get_type(), A_ovr::get_type()); // Working
	//factory.set_type_override_by_name("B", "B_override"); // Working
	//factory.set_inst_override_by_type(A::get_type(), A_override::get_type(), {get_full_name, ".", "env.a3"});
	//factory.set_inst_override_by_name("B", "B_ovr", "path1.b1");
	factory.print(); // This will print info about overridden classes.
	endfunction : build_phase
	endclass : test
	module top();
	initial begin
	run_test("test");
	end
	endmodule : top

view raw override_by_cmd_line.sv hosted with ❤ by GitHub

-------------------------------------------------------

Simulation time argument:
+uvm_set_inst_override=A,A_override,uvm_test_top.env.a3 \
+uvm_set_inst_override=B,B_ovr,path1.b1 \
+uvm_set_type_override=A,A_ovr \
+uvm_set_type_override=B,B_override
-------------------------------------------------------

	UVM_INFO @ 0: reporter [RNTST] Running test test...
	UVM_INFO @ 0: reporter [INSTOVR] Applying instance override from the command line: +uvm_set_inst_override=A,A_override,uvm_test_top.env.a3
	UVM_INFO @ 0: reporter [INSTOVR] Applying instance override from the command line: +uvm_set_inst_override=B,B_ovr,path1.b1
	UVM_INFO @ 0: reporter [UVM_CMDLINE_PROC] Applying type override from the command line: +uvm_set_type_override=A,A_ovr
	UVM_INFO @ 0: reporter [UVM_CMDLINE_PROC] Applying type override from the command line: +uvm_set_type_override=B,B_override
	UVM_INFO testbench.sv(122) @ 0: uvm_test_top [uvm_test_top] TEST set_inst_override_by_name
	#### Factory Configuration (*)
	Instance Overrides:
	Requested Type Override Path Override Type
	-------------- ------------------- -------------
	A uvm_test_top.env.a3 A_override
	B path1.b1 B_ovr
	Type Overrides:
	Requested Type Override Type
	-------------- -------------------
	A A_ovr
	B B_override
	All types registered with the factory: 46 total
	(types without type names will not be printed)
	Type Name
	---------
	A
	A_override
	A_ovr
	B
	B_override
	B_ovr
	environment
	snps_uvm_reg_bank_group
	snps_uvm_reg_map
	test
	(*) Types with no associated type name will be printed as <unknown>
	####
	UVM_INFO testbench.sv(7) @ 0: uvm_test_top.env.a1 [uvm_test_top.env.a1] A new
	UVM_INFO testbench.sv(20) @ 0: uvm_test_top.env.a1 [uvm_test_top.env.a1] A_ovr new
	UVM_INFO testbench.sv(7) @ 0: uvm_test_top.env.a2 [uvm_test_top.env.a2] A new
	UVM_INFO testbench.sv(20) @ 0: uvm_test_top.env.a2 [uvm_test_top.env.a2] A_ovr new
	UVM_INFO testbench.sv(7) @ 0: uvm_test_top.env.a3 [uvm_test_top.env.a3] A new
	UVM_INFO testbench.sv(33) @ 0: uvm_test_top.env.a3 [uvm_test_top.env.a3] A_override new
	UVM_INFO testbench.sv(47) @ 0: reporter [B_ovr] B new
	UVM_INFO testbench.sv(60) @ 0: reporter [B_ovr] B_ovr new
	UVM_INFO testbench.sv(47) @ 0: reporter [B_override] B new
	UVM_INFO testbench.sv(60) @ 0: reporter [B_override] B_ovr new
	UVM_INFO testbench.sv(73) @ 0: reporter [B_override] B_override new
	UVM_INFO testbench.sv(47) @ 0: reporter [B_override] B new
	UVM_INFO testbench.sv(60) @ 0: reporter [B_override] B_ovr new
	UVM_INFO testbench.sv(73) @ 0: reporter [B_override] B_override new
	UVM_INFO testbench.sv(24) @ 0: uvm_test_top.env.a1 [uvm_test_top.env.a1] HELLO from override class 'A_ovr'
	UVM_INFO testbench.sv(24) @ 0: uvm_test_top.env.a2 [uvm_test_top.env.a2] HELLO from override class 'A_ovr'
	UVM_INFO testbench.sv(37) @ 0: uvm_test_top.env.a3 [uvm_test_top.env.a3] HELLO from override class 'A_override'
	UVM_INFO testbench.sv(64) @ 0: reporter [b1] HELLO from override class 'B_ovr'
	UVM_INFO testbench.sv(77) @ 0: reporter [b2] HELLO from override class 'B_override'
	UVM_INFO testbench.sv(77) @ 0: reporter [b3] HELLO from override class 'B_override'

view raw override_by_cmd_line_op.sv hosted with ❤ by GitHub

-------------------------------------------------------

Singleton class in System Verilog

Sometimes it is required to have only one object of some classes like configuration classes. For this purpose we create singleton classes.
Only one object is created for a singleton class and whenever we try to create a new object, same object is returned.

System verilog does not provide construct to create a singleton class. But we can create it with some manipulation.

---------------------------------------------------------------------

	class singleton;
	int unsigned var1;
	// Need to declare it as static,
	// as it is accessed by static method 'create'
	static singleton single;
	// Declared as 'protected',
	// so user can't directly create instance of this class
	protected function new();
	endfunction : new
	// Make it static,
	// so user can use it before class is constructed
	// To create instance of this class first time when this it is not create
	static function singleton create();
	if (single == null) begin
	$display("Object single is null, so creating new object");
	single = new();
	end
	return single;
	endfunction : create
	endclass : singleton
	module top();
	singleton s1, s2;
	initial begin
	// create is static method so we can use it directly
	// using <class_name :: method_name>
	s1 = singleton :: create();
	$display (" 1 : s1.var1 = %0d", s1.var1);
	s1.var1 = 10;
	$display (" 2 : s1.var1 = %0d", s1.var1);
	s2 = singleton :: create();
	$display (" 3 : s2.var1 = %0d", s2.var1);
	s2.var1 = 20;
	$display (" 4 : s2.var1 = %0d", s2.var1);
	$display (" 5 : s1.var1 = %0d", s1.var1);
	end
	endmodule : top
	//Output:
	// Object single is null, so creating new object
	// 1 : s1.var1 = 0
	// 2 : s1.var1 = 10
	// 3 : s2.var1 = 10
	// 4 : s2.var1 = 20
	// 5 : s1.var1 = 20

view raw singleton.sv hosted with ❤ by GitHub

---------------------------------------------------------------------


uvm_root class defined as a singleton class in UVM source code.
---------------------------------------------------------------------

	// Snippet of UVM souce code for singleton
	virtual class uvm_coreservice_t;
	local static `UVM_CORESERVICE_TYPE inst;
	static function uvm_coreservice_t get();
	if(inst==null)
	inst=new;
	return inst;
	endfunction // get
	pure virtual function uvm_root get_root();
	endclass
	class uvm_default_coreservice_t extends uvm_coreservice_t;
	pure virtual function uvm_root get_root();
	virtual function uvm_root get_root();
	return uvm_root::m_uvm_get_root();
	endfunction
	endclass
	class uvm_root extends uvm_component;
	// singleton handle
	static local uvm_root m_inst;
	extern protected function new ();
	function uvm_root::new();
	super.new("__top__", null);
	m_rh.set_name("reporter");
	clp = uvm_cmdline_processor::get_inst();
	report_header();
	// This sets up the global verbosity. Other command line args may
	// change individual component verbosity.
	m_check_verbosity();
	endfunction
	// internal function not to be used
	// get the initialized singleton instance of uvm_root
	static function uvm_root m_uvm_get_root();
	if (m_inst == null) begin
	m_inst = new();
	void'(uvm_domain::get_common_domain());
	m_inst.m_domain = uvm_domain::get_uvm_domain();
	end
	return m_inst;
	endfunction
	uvm_coreservice_t cs;
	extern static function uvm_root get();
	function uvm_root uvm_root::get();
	uvm_coreservice_t cs = uvm_coreservice_t::get();
	return cs.get_root();
	endfunction
	endclass

view raw singleton_uvm.sv hosted with ❤ by GitHub

---------------------------------------------------------------------

UVM FAQ2

Why phasing is used? What are the different phases in uvm?

UVM Phases is used to control the behavior of simulation in a systematic way & execute in a sequential ordered to avoid race condition. This could also be done in system verilog but manually.

 

Which phases of UVM are Top-Down?
build_phase() & final_phase() are Top-Down, rest all phases are Bottom-Up.

Which phases of UVM are task?

run_phase(),
pre_reset_phase(), reset_phase(), post_reset_phase(),
pre_configure_phase(), configure_phase(), post_configure_phase(),
pre_main_phase(), main_phase(), post_main_phase(),
pre_shutdown_phase(), shutdown_phase(), post_shutdown_phase()

How do uvm phases initiate?

Calling run_test() constructs the UVM environment root component and then initiates the UVM phasing.

Why is the build_phase() in UVM executed in a Top - Down fashion and the other phases in Bottom - Up fashion?

The build phase has to be that way because the parent component's build_phase constructs the child components. You couldn't call the child's build_phase before the parent's build_phase because they the child objects haven't been constructed yet. You need a constructed object to call its method.

The build_phase() is also executed top-down so that the parent can provide override setting that the children will use when they execute their build_phase()

The ordering within the other phases should not matter, except you might want know that the top level's report_phase comes last.

What is the order of execution of run_phase() ?

The run_phase() of each component is executed concurrently with no defined order you can depend on.

During the run_phase() is there something like super.run_phase(phase) called?

You only need to call super.method() if you are extending a class an need the functionality of the base method. There is nothing inside the run_phase() of a uvm_component, so there is no need to call super.run_phase() when extending from it.

You may want to call it when extending your classes from your base classes.

What is the difference between run_phase and main_phase in uvm_component?

Actually, you can start a sequence in any phase. It is more important to understand the domain/scheduling relationships between the task based (i.e. runtime) phases.

UVM undergoes a number of pre-simulation phases (build, connect, end_of_elaboration, start_of_simulation) that are all implemented with functions. Once those are completed, the task based phases begin.

The standard includes two schedules.

• One is simply the run_phase, which starts executing at time zero and continues until all components have dropped their objections within the run_phase.
• The other schedule contains twelve phases that execute parallel to the run phase. They are: pre_reset, reset, post_reset, pre_config, config, post_config, pre_main, main, post_main, pre_shutdown, shutdown, and post_shutdown. They execute in sequence.

Every component has the opportunity to define or not define tasks to execute these phases. A phase starts only when all components in the previous phase have dropped their objections. A phase continues to execute until all components have dropped their objections in the current phase.

Why connect_phase() is bottom-up?

 

Difference between m_sequencer and p_sequencer in UVM

To understand difference between m_sequencer and p_sequencer, let's first go through couple of classes from UVM library.
-------------------------------------------------------------------------------------

	// Snippet of uvm_sequence_item class
	class uvm_sequence_item extends uvm_transaction;
	protected uvm_sequencer_base m_sequencer;
	protected uvm_sequence_base m_parent_sequence;
	// Set the sequence and sequencer execution context for a sequence item
	function void set_item_context(uvm_sequence_base parent_seq,
	uvm_sequencer_base sequencer = null);
	set_use_sequence_info(1);
	if (parent_seq != null) set_parent_sequence(parent_seq);
	if (sequencer == null && m_parent_sequence != null) sequencer = m_parent_sequence.get_sequencer();
	set_sequencer(sequencer);
	if (m_parent_sequence != null) set_depth(m_parent_sequence.get_depth() + 1);
	reseed();
	endfunction
	// Sets the default sequencer for the sequence to sequencer. It will take
	// effect immediately, so it should not be called while the sequence is
	// actively communicating with the sequencer.
	virtual function void set_sequencer(uvm_sequencer_base sequencer);
	m_sequencer = sequencer;
	m_set_p_sequencer();
	endfunction
	endclass

view raw m_sequencer_vs_p_sequencer_1.sv hosted with ❤ by GitHub

-------------------------------------------------------------------------------------


-------------------------------------------------------------------------------------

	// Snippet of uvm_sequence_base class
	class uvm_sequence_base extends uvm_sequence_item;
	// Executes this sequence, returning when the sequence has completed.
	//
	// The ~sequencer~ argument specifies the sequencer on which to run this
	// sequence. The sequencer must be compatible with the sequence.
	virtual task start (uvm_sequencer_base sequencer,
	uvm_sequence_base parent_sequence = null,
	int this_priority = -1,
	bit call_pre_post = 1);
	set_item_context(parent_sequence, sequencer);
	...
	endtask
	endclass
	// `uvm_declare_p_sequencer macro definition
	//
	// This macro is used to declare a variable ~p_sequencer~ whose type is
	// specified by ~SEQUENCER~.
	`define uvm_declare_p_sequencer(SEQUENCER) \
	SEQUENCER p_sequencer;\
	virtual function void m_set_p_sequencer();\
	super.m_set_p_sequencer(); \
	if( !$cast(p_sequencer, m_sequencer)) \
	`uvm_fatal("DCLPSQ", \
	$sformatf("%m %s Error casting p_sequencer, please verify that this sequence/sequence item is intended to execute on this type of sequencer", get_full_name())) \
	endfunction

view raw m_sequencer_vs_p_sequencer_2.sv hosted with ❤ by GitHub

-------------------------------------------------------------------------------------

When you call `uvm_declare_p_sequencer from sequence, it overrides m_set_p_sequencer function.
When you call start method of sequence, it calls set_item_context method,
Then set_item_context method calls set_sequencer method,
Then set_sequencer method assign handle of sequencer (which you pass in start method of sequence) to m_sequencer,
set_sequencer also calls m_set_p_sequencer method, but you have override the m_set_p_sequencer method by declaring `uvm_declare_p_sequencer macro.
So m_set_p_sequencer defined in macro will be executed, and it casts m_sequencer into p_sequencer,
where p_sequencer's type is specified by the argument of `uvm_declare_p_sequencer macro.

Conclusion:

m_sequencer and p_sequencer both point to the same thing (the sequencer on which the sequence is running). However, there are some important differences:
m_sequencer is a generic uvm sequencer pointer of type uvm_sequencer_base. It will always exist for an uvm_sequence and is initialized when the sequence is started.

p_sequencer is a reference to uvm_sequencer#(REQ,RSP), the user derived parameterized sequencer class.
Other way you can say that p_sequencer is a type specific sequencer pointer.
p_sequencer will not exist if the `uvm_declare_p_sequencer macros aren't used.

Advantage of p_sequencer over m_sequencer:
Being type specific, you will be able to access anything added to the sequencer (i.e. pointers to other sequencers, handle of environment class (which is defined in user derived virtual sequencer class) etc.).

Drawback of p_sequencer over m_sequencer:
p_sequencer creates an additional dependency, means sequence which use p_sequencer may not be executed on all the sequencers. Sequence requires resource in sequencer class which is declared as p_sequencer (i.e. pointers to other sequencers, handle of environment class, etc.)

Randomize Non-random (State) variable using randomize() method of Class

The randomize() method can be used to temporarily control the set of random and state variables within a class instance or object.

When randomize is called with arguments, those arguments designate the complete set of random variables within that object; all other variables in the object are considered state variables.

The randomize method accepts the special argument null to indicate no random variables for the duration of the call. In other words, all class members behave as state variables.

Consider following Example:

----------------------------------------------------

	class rand_mo;
	rand integer Var1;
	integer Var2;
	endclass
	program rand_mo_p_38;
	rand_mo obj = new();
	initial begin
	// Random variable: Var1, State Variable: Var2
	void'(obj.randomize());
	$display(" 1 : Var1 : %0d, Var2 : %0d",obj.Var1, obj.Var2);
	// Random variable: Var2, State Variable: Var1
	void'(obj.randomize(Var2));
	$display(" 2 : Var1 : %0d, Var2 : %0d",obj.Var1, obj.Var2);
	// Random variable: Var1, Var2
	void'(obj.randomize(Var1, Var2));
	$display(" 3 : Var1 : %0d, Var2 : %0d",obj.Var1, obj.Var2);
	// State variable: Var1, Var2
	void'(obj.randomize(null));
	$display(" 4 : Var1 : %0d, Var2 : %0d",obj.Var1, obj.Var2);
	end
	endprogram
	// Output:
	// 1 : Var1 : -902462825, Var2 : x
	// 2 : Var1 : -902462825, Var2 : -1241023056
	// 3 : Var1 : 69704603, Var2 : -1877783293
	// 4 : Var1 : 69704603, Var2 : -1877783293

view raw randomize_with_arguments.sv hosted with ❤ by GitHub

----------------------------------------------------

rand_mode and constraint_mode in System Verilog

rand_mode:

The random nature of variables declared as rand or randc can be turned on or off dynamically by using in-built method called rand_mode().  rand_mode() can be called as function or task.

In below example, rand_mode of all variable of class is disabled and enabled.

---------------------------------------------------------------------

	class rand_mo;
	rand integer Var1;
	randc integer Var2;
	endclass
	program rand_mo_p_23;
	rand_mo obj = new();
	initial begin
	void'(obj.randomize());
	$display(" 1 : Var1 : %d, Var2 : %d ",obj.Var1, obj.Var2);
	// Var1 and Var2 will be treated as State variables.
	obj.rand_mode(0);
	void'(obj.randomize());
	$display(" 2 : Var1 : %d, Var2 : %d ",obj.Var1, obj.Var2);
	// Var1 and Var2 will be treated as random variables.
	obj.rand_mode(1);
	void'(obj.randomize());
	$display(" 3 : Var1 : %d, Var2 : %d ",obj.Var1, obj.Var2);
	end
	endprogram
	//Output:
	// 1 : Var1 : -902462825, Var2 : 906460592
	// 2 : Var1 : -902462825, Var2 : 906460592 //Remain same (not randomized)
	// 3 : Var1 : 69704603, Var2 : 1917593266

view raw rand_mode_1.sv hosted with ❤ by GitHub

---------------------------------------------------------------------

We can also change rand_mode of specific variable. Consider below example,

---------------------------------------------------------------------

	class rand_mo;
	rand integer Var1;
	rand integer Var2;
	endclass
	program rand_mo_p_24;
	rand_mo obj = new();
	initial begin
	void'(obj.randomize());
	$display(" 1 : Var1 : %d Var2 : %d ",obj.Var1,obj.Var2);
	// Var1 will become State variable
	obj.Var1.rand_mode(0);
	void'(obj.randomize());
	$display(" 2 : Var1 : %d Var2 : %d ",obj.Var1,obj.Var2);
	// Var2 will also become State variable
	obj.Var2.rand_mode(0);
	$display(" 3 : Var1 : %d Var2 : %d ",obj.Var1,obj.Var2);
	// Var1 will become random variable
	obj.Var1.rand_mode(1);
	void'(obj.randomize());
	$display(" 4 : Var1 : %d Var2 : %d ",obj.Var1,obj.Var2);
	end
	endprogram
	//Output:
	// 1 : Var1 : -902462825 Var2 : -1241023056 // Botn Var1 and Var2 are randomized
	// 2 : Var1 : -902462825 Var2 : 69704603 // Var1 remain unchanged (Not randomized)
	// 3 : Var1 : -902462825 Var2 : 69704603 // Var1 and Var2 both remain unchanged (Not randomized)
	// 4 : Var1 : -1877783293 Var2 : 69704603 // Var1 changed (randomized), Var2 reamin unchanged (Not randomized)

view raw rand_mode_2.sv hosted with ❤ by GitHub

---------------------------------------------------------------------

When rand_mode method is called as function, it returns the active status of the specified random variable.

When called as a function, rand_mode() returns the current active state of the specified random variable. It returns 1 if the variable is active (ON) and 0 if the variable is inactive (OFF).

---------------------------------------------------------------------

	class rand_mo;
	rand integer Var1;
	rand integer Var2;
	endclass
	program rand_mo_p_24;
	rand_mo obj = new();
	initial begin
	void'(obj.randomize());
	$display(" 1 : Var1 : %d Var2 : %d ",obj.Var1,obj.Var2);
	obj.Var1.rand_mode(0);
	void'(obj.randomize());
	$display(" 2 : Var1 : %d Var2 : %d ",obj.Var1,obj.Var2);
	if(obj.Var1.rand_mode()) begin
	$display(" 3a : Var1 is random");
	end
	else begin
	$display(" 3b : Var1 is nonrandom");
	end
	void'(obj.randomize());
	$display(" 4 : Var1 : %d Var2 : %d ",obj.Var1,obj.Var2);
	end
	endprogram
	//Output:
	// 1 : Var1 : -902462825 Var2 : -1241023056
	// 2 : Var1 : -902462825 Var2 : 69704603
	// 3b : Var1 is nonrandom
	// 4 : Var1 : -902462825 Var2 : -1877783293

view raw rand_mode_3.sv hosted with ❤ by GitHub

---------------------------------------------------------------------

A compiler error shall be issued if the specified variable does not exist within the class hierarchy or even though it exists but not declared as rand or randc. The following example illustrates the second case.

rand_mode of rand static variable,

---------------------------------------------------------------------

	class A;
	rand static integer Var1;
	rand integer Var2;
	endclass
	program A_p_27;
	A obj_1 = new;
	A obj_2 = new;
	initial begin
	obj_2.Var1.rand_mode(0);
	obj_2.Var2.rand_mode(0);
	repeat(2) begin
	void'(obj_1.randomize());
	$display(" 1 : obj_1.Var1 : %0d, obj_1.Var2 : %0d, obj_2.Var1 : %0d, obj_2.Var2 : %0d",obj_1.Var1,obj_1.Var2,obj_2.Var1,obj_2.Var2);
	void'(obj_2.randomize());
	$display(" 2 : obj_1.Var1 : %0d, obj_1.Var2 : %0d, obj_2.Var1 : %0d, obj_2.Var2 : %0d",obj_1.Var1,obj_1.Var2,obj_2.Var1,obj_2.Var2);
	end
	end
	endprogram
	//Output:
	// 1 : obj_1.Var1 : x, obj_1.Var2 : -902462825, obj_2.Var1 : x, obj_2.Var2 : x
	// 2 : obj_1.Var1 : x, obj_1.Var2 : -902462825, obj_2.Var1 : x, obj_2.Var2 : x
	// 1 : obj_1.Var1 : x, obj_1.Var2 : -1241023056, obj_2.Var1 : x, obj_2.Var2 : x
	// 2 : obj_1.Var1 : x, obj_1.Var2 : -1241023056, obj_2.Var1 : x, obj_2.Var2 : x

view raw rand_mode_4.sv hosted with ❤ by GitHub

---------------------------------------------------------------------

 

constraint_mode

SystemVerilog supports to change the status of constraint block dynamically.

The constraint_mode() method can be used to active/inactive constraint. By default all the constraint blocks are active. When a constraint is inactive, it is not considered by the randomize() method.

It can be used as task or function.

When called as a task, the argument to the constraint_mode task method determines the operation to be performed. 

When called as a function, constraint_mode() returns the current active state of the specified constraint block. It returns 1 if the constraint is active (ON) and 0 if the constraint is inactive (OFF).

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	// object_name.constraint_mode
	class rand_mo;
	rand integer Var1;
	rand integer Var2;
	constraint Var_1 { Var1 == 20;}
	constraint Var_2 { Var2 == 10;}
	endclass
	program rand_mo_p_38;
	rand_mo obj = new();
	initial begin
	//By default all constraints are active.
	void'(obj.randomize());
	$display(" 1 : Var1 : %0d, Var2 : %0d ",obj.Var1, obj.Var2);
	//Both constraints Var_1 and Var_2 are turned off.
	obj.constraint_mode(0);
	void'(obj.randomize());
	$display(" 2 : Var1 : %0d, Var2 : %0d ",obj.Var1, obj.Var2);
	//Both constraints Var_1 and Var_2 are turned on.
	obj.constraint_mode(1);
	void'(obj.randomize());
	$display(" 3 : Var1 : %0d, Var2 : %0d ",obj.Var1, obj.Var2);
	end
	endprogram
	//Output:
	// 1 : Var1 : 20, Var2 : 10
	// 2 : Var1 : -755415376, Var2 : -334455186
	// 3 : Var1 : 20, Var2 : 10

view raw constraint_mode_1.sv hosted with ❤ by GitHub

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	// object_name.constraint_name.constraint_mode
	class rand_mo;
	rand integer Var1;
	rand integer Var2;
	constraint Var_1 { Var1 == 20;}
	constraint Var_2 { Var2 == 10;}
	endclass
	program rand_mo_p_38;
	rand_mo obj = new();
	initial begin
	void'(obj.randomize());
	$display(" Var1 : %0d, Var2 : %0d ",obj.Var1, obj.Var2);
	obj.Var_1.constraint_mode(0);
	void'(obj.randomize());
	$display(" Var1 : %0d, Var2 : %0d ",obj.Var1, obj.Var2);
	obj.Var_1.constraint_mode(1);
	void'(obj.randomize());
	$display(" Var1 : %0d, Var2 : %0d ",obj.Var1, obj.Var2);
	end
	endprogram
	//Output:
	// Var1 : 20, Var2 : 10
	// Var1 : -755415376, Var2 : 10
	// Var1 : 20, Var2 : 10

view raw constraint_mode_2.sv hosted with ❤ by GitHub

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	// Used as Function
	class rand_mo;
	rand integer Var1;
	rand integer Var2;
	constraint Var_1 { Var1 == 20;}
	constraint Var_2 { Var2 == 10;}
	endclass
	program rand_mo_p_38;
	rand_mo obj = new();
	initial begin
	//By default all constraints are active.
	void'(obj.randomize());
	$display(" 1 : Var1 : %0d, Var2 : %0d",obj.Var1, obj.Var2);
	//Both constraint Var_1 is are turned off.
	obj.Var_1.constraint_mode(0);
	void'(obj.randomize());
	$display(" 2 : Var1 : %0d, Var2 : %0d",obj.Var1, obj.Var2);
	if (obj.Var_1.constraint_mode())
	$display(" 3a : Var_1 constraint si active");
	else
	$display(" 3b : Var_1 constraint si inactive");
	if (obj.Var_2.constraint_mode())
	$display(" 4a : Var_2 constraint si active");
	else
	$display(" 4b : Var_2 constraint si inactive");
	void'(obj.randomize());
	$display(" 5 : Var1 : %0d, Var2 : %0d ",obj.Var1, obj.Var2);
	end
	endprogram
	//Output:
	// 1 : Var1 : 20, Var2 : 10
	// 2 : Var1 : -755415376, Var2 : 10
	// 3b : Var_1 constraint si inactive
	// 4a : Var_2 constraint si active
	// 5 : Var1 : -334455186, Var2 : 10

view raw constraint_mode_3.sv hosted with ❤ by GitHub

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