Verification Engineer's Blog: February 2016

Thursday, 11 February 2016

uvm_config_db

The uvm_config_db class is the recommended way to access the resource database.

A resource is any piece of information that is shared between more than one component or object.

We use uvm_config_db::set to put something into the database and uvm_config_db::get to retrieve information from the database.

The uvm_config_db class is parameterized, so the database behaves as if it is partitioned into many type-specific "mini databases."

There are no limitations on the the type - it could be a class, a uvm_object, a built in type such as a bit, byte, or a virtual interface.

There are two typical uses for uvm_config_db. The first is to pass virtual interfaces from the DUT to the test, and the second is to pass configuration classes down through the testbench.

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	/***************************************************
	***** SET Method
	***************************************************/
	static function void set( uvm_component cntxt,
	string inst_name,
	string field_name,
	T value
	);

	// set function cannot return any value as its return type is "void".
	// So we cannot use if condition to check whether set is successfully
	// done or not.

	The full signature of the set method is
	void uvm_config_db #( type T = int )::set( uvm_component cntxt ,
	string inst_name ,
	string field_name ,
	T value );

view raw uvm_config_db1.sv hosted with ❤ by GitHub

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	/***************************************************
	***** GET Method
	***************************************************/

	static function bit get( uvm_component cntxt,
	string inst_name,
	string field_name,
	inout T value
	);

	// The method returns 1 if it is successful and
	// 0 if there is no such resource of this type at this location.

	The full signature of the get method is
	bit uvm_config_db #( type T = int )::get( uvm_component cntxt ,
	string inst_name ,
	string field_name ,
	ref T value );
	// value is the thing which is going to be retreived from the database.
	// If the call to get is successful, this value will be overwritten.
	// (that's why we use keyword "ref" here).

view raw uvm_config_db2.sv hosted with ❤ by GitHub

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/*****************ARGUMENTS*****************/

T is the type of the element being configured - usually a virtual interface or a configuration object.

cntxt and inst_name together form a scope that is used to locate the resource within the database.

The scope is formed by appending the instance name to the full hierarchical name of the context.

{cntxt, ".", inst_name}. or {cntxt.get_full_name(),".",inst_name}. //need to confirm

If cntxt is null then inst_name provides the complete scope information of the setting.

field_name is the key through which you can store and get that particular object.

field_name must be same during get & set, because while getting from uvm_databse it will find for field_name.

value is the thing or resource which is actually going to be put into the database.

value name can be different but value type must be same for get and set.

Both inst_name and field_name may be glob style or regular expression style expressions.

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	// ---------- Example1: ----------
	// FROM TOP file
	interface ahb_if data_port_if( clk , reset );
	uvm_config_db #( virtual ahb_if )::set( null , "*" , "data_port" , data_port_if );
	//-------Example1:
	// Here in inst_name, we use "uvm_test_top" because it is more precise and more efficient than "*".
	// This will always work unless your top level test does something other than super.new(name, parent)
	// in the constructor of your test component.
	// If you do something different in your test component, you will have to adjust the instance name accordingly.
	interface ahb_if control_port_if( clk , reset );
	uvm_config_db #( virtual ahb_if )::set( null , "uvm_test_top" , "control_port" , control_port_if );

	//-------Example2:
	// We can use uvm_root::get() variable also.
	uvm_config_db #( virtual ahb_if )::set( uvm_root::get(), "uvm_test_top" , "control_port" , control_port_if );

	//-------Example3:
	// We can set multiple instance of interface from TOP using generate block.
	interface Tx_intf[3];
	generate
	genvar i;
	for( i = 0; i < 3; i++) begin : TxifConfig
	initial begin
	// Set Virtual Interface to Database
	uvm_config_db#(virtual Tx_intf)::set(uvm_root::get(), "*", $sformatf("Tx_if[%0d]", i), Tx_if[i]);
	end
	end : TxifConfig
	endgenerate

view raw uvm_config_db3.sv hosted with ❤ by GitHub

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	//---------- Example2: ------------
	//-------Example4:
	// Get multiple instance of interface in class (Ex: env) using any LOOP (Ex: for, while)
	interface Tx_intf[3];
	...
	for (int unsigned i=0; i < 3; i++) begin
	if (!uvm_config_db #(router_Tx_agent_config)::get (this, "", $sformatf("Tx_cfg[%0d]", i), Tx_cfg[i]))
	`uvm_fatal ("NO-Tx_agnt_cfg", "agent config must be set for this class")
	end

	//-------Example5:
	// We can set mulitple instance of configuration object from TEST_CASE using LOOP (for, while)
	router_Tx_agent_config Tx_cfg[];
	...
	// allocate memory to dynamic array of configuration object from test_case build_phase
	for (int unsigned i=0; i<3; i++)
	Tx_cfg[i] = new ($sformatf("Tx_cfg[%0d]", i));

	// set Tx_agent_config from test_case build_phase
	for (int unsigned i=0; i<3; i++)
	uvm_config_db #(router_Tx_agent_config)::set (null, "*", $sformatf("Tx_cfg[%0d]", i), Tx_cfg[i]);

	//get Tx_agent_config in env build_phase
	for (int unsigned i=0; i<3; i++) begin
	if (!uvm_config_db #(router_Tx_agent_config)::get (this, "", $sformatf("Tx_cfg[%0d]", i), Tx_cfg[i]))
	`uvm_fatal ("NO-Tx_agnt_cfg", "agent config must be set for this class")
	end

	//-------Example6:
	//We set configuration objects from ENV
	router_Tx_agent_config Tx_cfg[3];
	// set agent config for agents
	for (int unsigned i=0; i<`RxNUM; i++) begin
	uvm_config_db #(router_Tx_agent_config)::set (null, $sformatf("Tx_agnt[%0d]", i), $sformatf("Tx_cfg[%0d]", i), Tx_cfg[i]);
	end

	// We get configuration objects in AGENT
	// Handle of agent config
	router_Tx_agent_config Tx_cfg;

	// get agent_config
	if (!uvm_config_db #(router_Tx_agent_config)::get (this, "", $sformatf("Tx_cfg[%0d]", idx), Tx_cfg))
	`uvm_fatal ("NO-Tx_agnt_cfg", "agent config must be set for this class")

	// 3rd argument field_name must be same in get and set.
	//"idx" is agent_id set by env.
	// build child components
	//for (int unsigned i = 0; i < env_cfg.num_of_Tx_agent; i++) begin
	// Tx_agnt[i] = router_Tx_agent::type_id::create($sformatf("Tx_agnt[%0d]", i), this);
	// Tx_agnt[i].idx = i;
	//end

view raw uvm_config_db4.sv hosted with ❤ by GitHub

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	//-------Example7:
	// We use "m_ahb_agent*" to ensure that we config both the agent and its children.
	// Without the '*' we would only configure the agent itself and not the driver, sequencer and monitor inside it.
	uvm_config_db #( ahb_agent_config )::set( null , "m_ahb_agent*" , "ahb_agent_config" , ahb_agent_config_h );

	//-------Example8:
	if( !uvm_config_db #( virtual ahb_if )::get( this , "" , "data_port" , m_cfg.m_data_port_config.m_ahb_if ) ) begin
	`uvm_error("Config Error" , "uvm_config_db #( virtual ahb_if )::get cannot find resource data_port" ) )
	end

view raw uvm_config_db5.sv hosted with ❤ by GitHub

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Precedence:

Build Phase:

----------------------------------------------------------------------------------------------------------------------

	/***************PRECEDENCE at BUILD TIME***************/
	// If a setting is made at build time, the cntxt hierarchy is
	// used to determine the setting's precedence in the database.
	// Settings from hierarchically higher levels have higher precedence.

	// Settings from the same level of hierarchy have a last setting wins
	// semantic.

	// A precedence setting of "uvm_resource_base::default_precedence" is
	// used for uvm_top,
	// and each hierarcical level below the top is decremented by 1.

	// Example1:
	// take one variable "int var1".
	// We set this variable from build_phase of test_case with value 70.
	var1 = 70;
	uvm_config_db #(int)::set (this, "*", "var1", var1);

	// We set this variable from build_phase of env with value 60.
	var1 = 60;
	uvm_config_db #(int)::set (this, "*", "var1", var1);

	// We set this variable from build_phase of agent with value 40.
	var1 = 40;
	uvm_config_db #(int)::set (this, "*", "var1", var1);

	// We get this variable in build_phase of driver.
	uvm_config_db #(int)::get(this, "", "var1", var1);
	$display("DRIVER var1=%0d", var1);

	//OutPut of $display Statement is 70. (highest hierarchy win)
	// (Settings from hierarchically higher levels have higher precedence)


	//Example2:
	// take one variable "int var1".
	// We set this variable from build_phase of test_case with value 70.
	var1 = 70;
	uvm_config_db #(int)::set (null, "*", "var1", var1);

	// We set this variable from build_phase of env with value 60.
	var1 = 60;
	uvm_config_db #(int)::set (null, "*", "var1", var1);

	// We set this variable from build_phase of agent with value 40.
	var1 = 40;
	uvm_config_db #(int)::set (null, "*", "var1", var1);

	// We get this variable in build_phase of driver.
	uvm_config_db #(int)::get(this, "", "var1", var1);
	$display("DRIVER var1=%0d", var1);

	// OutPut of $display Statement is 40. (highest hierarchy win)
	// (Settings from hierarchically higher levels have higher precedence)

	// Here during set we have not give any cntxt hierarchy,
	// so it will get form its parent.
	// If its parent had not set any value then child will get
	// value from its parent's parent and so on...

view raw uvm_config_db_build1.sv hosted with ❤ by GitHub

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Example1:

----------------------------------------------------------------------------------------------------------------------

	`include "uvm.sv"
	import uvm_pkg :: *;

	class my_agent extends uvm_agent;
	`uvm_component_utils (my_agent)
	int var1;

	function new (string name = "my_agent", uvm_component parent = null);
	super.new(name, parent);
	endfunction

	function void build_phase (uvm_phase phase);
	super.build_phase (phase);
	if(!uvm_config_db #(int)::get(this, "", "var1", var1))
	`uvm_error ("GET-FAIL", "not able to get value")
	else
	`uvm_info ("GET-PASS", $sformatf("var1=%0d", var1), UVM_NONE)
	endfunction

	task run_phase (uvm_phase phase);
	endtask
	endclass

	/////////////////
	class my_env extends uvm_env;
	`uvm_component_utils (my_env)
	int var1;
	my_agent agnt;

	function new (string name = "my_env", uvm_component parent = null);
	super.new(name, parent);
	endfunction

	function void build_phase (uvm_phase phase);
	super.build_phase (phase);
	agnt = my_agent::type_id::create("angt", this);
	var1 = 60;
	uvm_config_db #(int)::set(this, "*", "var1", var1);
	`uvm_info ("SET", $sformatf("From ENV=%0d", var1), UVM_NONE)
	endfunction

	task run_phase (uvm_phase phase);
	endtask
	endclass

	/////////////////
	class my_test extends uvm_test;
	`uvm_component_utils (my_test)
	int var1;
	my_env env;

	function new (string name = "my_test", uvm_component parent = null);
	super.new(name, parent);
	endfunction

	function void build_phase (uvm_phase phase);
	super.build_phase (phase);
	env = my_env::type_id::create("env", this);
	var1 = 70;
	uvm_config_db #(int)::set(this, "*", "var1", var1);
	`uvm_info ("SET", $sformatf("From TEST=%0d", var1), UVM_NONE)
	endfunction

	task run_phase (uvm_phase phase);
	phase.raise_objection(this);
	#500;
	phase.drop_objection(this);
	endtask
	endclass

	module top();
	initial begin
	run_test("my_test");
	end
	endmodule

	//Output:
	// UVM_INFO @ 0: reporter [RNTST] Running test my_test...
	// UVM_INFO top.sv(63) @ 0: uvm_test_top [SET] From TEST=70
	// UVM_INFO top.sv(41) @ 0: uvm_test_top.env [SET] From ENV=60
	// UVM_INFO top.sv(19) @ 0: uvm_test_top.env.angt [GET-PASS] var1=70

view raw uvm_config_db_build_null.sv hosted with ❤ by GitHub

----------------------------------------------------------------------------------------------------------------------

Example2:

----------------------------------------------------------------------------------------------------------------------

	`include "uvm.sv"
	import uvm_pkg :: *;

	class my_agent extends uvm_agent;
	`uvm_component_utils (my_agent)
	int var1;

	function new (string name = "my_agent", uvm_component parent = null);
	super.new(name, parent);
	endfunction

	function void build_phase (uvm_phase phase);
	super.build_phase (phase);
	// if(!uvm_config_db #(int)::get(this, "", "var1", var1))
	// `uvm_error ("GET-FAIL", "not able to get value")
	// else
	// `uvm_info ("GET-PASS", $sformatf("var1=%0d", var1), UVM_NONE)
	endfunction

	task run_phase (uvm_phase phase);
	#80;
	if(!uvm_config_db #(int)::get(this, "", "var1", var1))
	`uvm_error ("GET-FAIL", "not able to get value")
	else
	`uvm_info ("GET-PASS", $sformatf("var1=%0d", var1), UVM_NONE)
	endtask
	endclass

	/////////////////
	class my_env extends uvm_env;
	`uvm_component_utils (my_env)
	int var1;
	my_agent agnt;

	function new (string name = "my_env", uvm_component parent = null);
	super.new(name, parent);
	endfunction

	function void build_phase (uvm_phase phase);
	super.build_phase (phase);
	agnt = my_agent::type_id::create("angt", this);
	// var1 = 60;
	// uvm_config_db #(int)::set(this, "*", "var1", var1);
	// `uvm_info ("SET", $sformatf("From ENV=%0d", var1), UVM_NONE)
	endfunction

	task run_phase (uvm_phase phase);
	// #75;
	#60
	var1 = 60;
	uvm_config_db #(int)::set(this, "*", "var1", var1);
	`uvm_info ("SET", $sformatf("From ENV=%0d", var1), UVM_NONE)
	endtask
	endclass

	/////////////////
	class my_test extends uvm_test;
	`uvm_component_utils (my_test)
	int var1;
	my_env env;

	function new (string name = "my_test", uvm_component parent = null);
	super.new(name, parent);
	endfunction

	function void build_phase (uvm_phase phase);
	super.build_phase (phase);
	env = my_env::type_id::create("env", this);
	// var1 = 70;
	// uvm_config_db #(int)::set(this, "*", "var1", var1);
	// `uvm_info ("SET", $sformatf("From TEST=%0d", var1), UVM_NONE)
	endfunction

	task run_phase (uvm_phase phase);
	phase.raise_objection(this);
	#70;
	var1 = 70;
	uvm_config_db #(int)::set(this, "*", "var1", var1);
	`uvm_info ("SET", $sformatf("From TEST=%0d", var1), UVM_NONE)
	#500;
	phase.drop_objection(this);
	endtask
	endclass

	module top();
	initial begin
	run_test("my_test");
	end
	endmodule

	//Output:
	// UVM_INFO @ 0: reporter [RNTST] Running test my_test...
	// UVM_INFO top.sv(55) @ 60: uvm_test_top.env [SET] From ENV=60
	// UVM_INFO top.sv(82) @ 70: uvm_test_top [SET] From TEST=70
	// UVM_INFO top.sv(28) @ 80: uvm_test_top.env.angt [GET-PASS] var1=70

view raw uvm_config_db_run_this.sv hosted with ❤ by GitHub

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Run Phase:

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	/***************PRECEDENCE at RUN TIME (AFTER BUILD)***************/
	// After build time, all settings use the default precedence
	// and thus have a last wins semantic.
	// So, if at run time, a low level component makes a runtime setting
	// of some field, that setting will have precedence over a setting
	// from the test level that was made earlier in the simulation.

	// Example1:
	// take one variable "int var1".
	// We set this variable from run_phase of test_case with value 70.
	#70;
	var1 = 70;
	uvm_config_db #(int)::set (null/this, "*", "var1", var1);

	// We set this variable from run_phase of env with value 60.
	#60;
	var1 = 60;
	uvm_config_db #(int)::set (null/this, "*", "var1", var1);

	// We get this variable from run_phase of agent.
	#80;
	uvm_config_db #(int)::get (this, "", "var1", var1);

	// Output:
	// We got Latest value. Here 70.


	// Example2:
	// take one variable "int var1".
	// We set this variable from run_phase of test_case with value 70.
	#70;
	var1 = 70;
	uvm_config_db #(int)::set (null/this, "*", "var1", var1);

	// We set this variable from run_phase of env with value 60.
	#75;
	var1 = 60;
	uvm_config_db #(int)::set (null/this, "*", "var1", var1);

	// We get this variable from run_phase of agent.
	#80;
	uvm_config_db #(int)::get (this, "", "var1", var1);

	// Output:
	// We got Latest value. Here 60.

view raw uvm_config_db_run1.sv hosted with ❤ by GitHub

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Example1:

----------------------------------------------------------------------------------------------------------------------

	`include "uvm.sv"
	import uvm_pkg :: *;

	class my_agent extends uvm_agent;
	`uvm_component_utils (my_agent)
	int var1;

	function new (string name = "my_agent", uvm_component parent = null);
	super.new(name, parent);
	endfunction

	function void build_phase (uvm_phase phase);
	super.build_phase (phase);
	// if(!uvm_config_db #(int)::get(this, "", "var1", var1))
	// `uvm_error ("GET-FAIL", "not able to get value")
	// else
	// `uvm_info ("GET-PASS", $sformatf("var1=%0d", var1), UVM_NONE)
	endfunction

	task run_phase (uvm_phase phase);
	#80;
	if(!uvm_config_db #(int)::get(this, "", "var1", var1))
	`uvm_error ("GET-FAIL", "not able to get value")
	else
	`uvm_info ("GET-PASS", $sformatf("var1=%0d", var1), UVM_NONE)
	endtask
	endclass

	/////////////////
	class my_env extends uvm_env;
	`uvm_component_utils (my_env)
	int var1;
	my_agent agnt;

	function new (string name = "my_env", uvm_component parent = null);
	super.new(name, parent);
	endfunction

	function void build_phase (uvm_phase phase);
	super.build_phase (phase);
	agnt = my_agent::type_id::create("angt", this);
	// var1 = 60;
	// uvm_config_db #(int)::set(this, "*", "var1", var1);
	// `uvm_info ("SET", $sformatf("From ENV=%0d", var1), UVM_NONE)
	endfunction

	task run_phase (uvm_phase phase);
	// #75;
	#60
	var1 = 60;
	uvm_config_db #(int)::set(this, "*", "var1", var1);
	`uvm_info ("SET", $sformatf("From ENV=%0d", var1), UVM_NONE)
	endtask
	endclass

	/////////////////
	class my_test extends uvm_test;
	`uvm_component_utils (my_test)
	int var1;
	my_env env;

	function new (string name = "my_test", uvm_component parent = null);
	super.new(name, parent);
	endfunction

	function void build_phase (uvm_phase phase);
	super.build_phase (phase);
	env = my_env::type_id::create("env", this);
	// var1 = 70;
	// uvm_config_db #(int)::set(this, "*", "var1", var1);
	// `uvm_info ("SET", $sformatf("From TEST=%0d", var1), UVM_NONE)
	endfunction

	task run_phase (uvm_phase phase);
	phase.raise_objection(this);
	#70;
	var1 = 70;
	uvm_config_db #(int)::set(this, "*", "var1", var1);
	`uvm_info ("SET", $sformatf("From TEST=%0d", var1), UVM_NONE)
	#500;
	phase.drop_objection(this);
	endtask
	endclass

	module top();
	initial begin
	run_test("my_test");
	end
	endmodule

	//Output:
	// UVM_INFO @ 0: reporter [RNTST] Running test my_test...
	// UVM_INFO top.sv(55) @ 60: uvm_test_top.env [SET] From ENV=60
	// UVM_INFO top.sv(82) @ 70: uvm_test_top [SET] From TEST=70
	// UVM_INFO top.sv(28) @ 80: uvm_test_top.env.angt [GET-PASS] var1=70

view raw uvm_config_db_run_this.sv hosted with ❤ by GitHub

----------------------------------------------------------------------------------------------------------------------

Example2:

----------------------------------------------------------------------------------------------------------------------

	class my_agent extends uvm_agent;
	`uvm_component_utils (my_agent)
	int var1;

	function new (string name = "my_agent", uvm_component parent = null);
	super.new(name, parent);
	endfunction

	function void build_phase (uvm_phase phase);
	super.build_phase (phase);
	// if(!uvm_config_db #(int)::get(null, "", "var1", var1))
	// `uvm_error ("GET-FAIL", "not able to get value")
	// else
	// `uvm_info ("GET-PASS", $sformatf("var1=%0d", var1), UVM_NONE)
	endfunction

	task run_phase (uvm_phase phase);
	#80;
	if(!uvm_config_db #(int)::get(this, "", "var1", var1))
	`uvm_error ("GET-FAIL", "not able to get value")
	else
	`uvm_info ("GET-PASS", $sformatf("var1=%0d", var1), UVM_NONE)
	endtask
	endclass

	/////////////////
	class my_env extends uvm_env;
	`uvm_component_utils (my_env)
	int var1;
	my_agent agnt;

	function new (string name = "my_env", uvm_component parent = null);
	super.new(name, parent);
	endfunction

	function void build_phase (uvm_phase phase);
	super.build_phase (phase);
	agnt = my_agent::type_id::create("angt", this);
	// var1 = 60;
	// uvm_config_db #(int)::set(null, "*", "var1", var1);
	// `uvm_info ("SET", $sformatf("From ENV=%0d", var1), UVM_NONE)
	endfunction

	task run_phase (uvm_phase phase);
	// #75;
	#60;
	var1 = 60;
	uvm_config_db #(int)::set(null, "*", "var1", var1);
	`uvm_info ("SET", $sformatf("From ENV=%0d", var1), UVM_NONE)
	endtask
	endclass

	/////////////////
	class my_test extends uvm_test;
	`uvm_component_utils (my_test)
	int var1;
	my_env env;

	function new (string name = "my_test", uvm_component parent = null);
	super.new(name, parent);
	endfunction

	function void build_phase (uvm_phase phase);
	super.build_phase (phase);
	env = my_env::type_id::create("env", this);
	// var1 = 70;
	// uvm_config_db #(int)::set(null, "*", "var1", var1);
	// `uvm_info ("SET", $sformatf("From TEST=%0d", var1), UVM_NONE)
	endfunction

	task run_phase (uvm_phase phase);
	phase.raise_objection(this);
	#70;
	var1 = 70;
	uvm_config_db #(int)::set(null, "*", "var1", var1);
	`uvm_info ("SET", $sformatf("From TEST=%0d", var1), UVM_NONE)
	#500;
	phase.drop_objection(this);
	endtask
	endclass

	module top();
	initial begin
	run_test("my_test");
	end
	endmodule

	//Output:
	// UVM_INFO @ 0: reporter [RNTST] Running test my_test...
	// UVM_INFO top.sv(54) @ 60: uvm_test_top.env [SET] From ENV=60
	// UVM_INFO top.sv(81) @ 70: uvm_test_top [SET] From TEST=70
	// UVM_INFO top.sv(27) @ 80: uvm_test_top.env.angt [GET-PASS] var1=70

view raw uvm_config_db_run_null.sv hosted with ❤ by GitHub

----------------------------------------------------------------------------------------------------------------------

/*********************Guideline**************************/

1. Before set anything into database first allocates memory to them and then put into database using set method.

Friday, 5 February 2016

`uvm_info vs uvm_report_info in SystemVerilog

--------------------------------------------------------------------------------------------

	`include "uvm.sv"
	import uvm_pkg :: *;

	class base;
	rand int unsigned a;
	endclass

	program main;
	base B;

	initial begin
	B = new();
	B.randomize();
	`uvm_info ("UVM_INFO", $sformatf("a=%0d", B.a), UVM_NONE)
	uvm_report_info ("UVM_REPORT_INFO", $sformatf("a=%0d", B.a), UVM_NONE);
	end
	endprogram : main

	//Output:
	// UVM_INFO top.sv(14) @ 0: reporter [UVM_INFO] a=727460974
	// UVM_INFO @ 0: reporter [UVM_REPORT_INFO] a=727460974


	//-------------uvm_report_catcher.svh-----------------
	// virtual function void uvm_report_info(
	// string id,
	// string message,
	// int verbosity,
	// string fname = "", // filename
	// int line = 0);
	//
	// virtual function void uvm_report_warning(
	// string id,
	// string message,
	// int verbosity,
	// string fname = "",
	// int line = 0);
	//
	// virtual function void uvm_report_error(
	// string id,
	// string message,
	// int verbosity,
	// string fname = "",
	// int line = 0);
	//
	// virtual function void uvm_report_fatal(
	// string id,
	// string message,
	// int verbosity,
	// string fname = "",
	// int line = 0);


	//-------------uvm_message_defines.svh-----------------
	// `ifdef UVM_REPORT_DISABLE_FILE
	// `define uvm_file ""
	// `else
	// `define uvm_file `__FILE__
	// `endif
	//
	// `ifdef UVM_REPORT_DISABLE_LINE
	// `define uvm_line 0
	// `else
	// `define uvm_line `__LINE__
	// `endif
	//
	// `define uvm_info(ID,MSG,VERBOSITY) \
	// begin \
	// if (uvm_report_enabled(VERBOSITY,UVM_INFO,ID)) \
	// uvm_report_info (ID, MSG, VERBOSITY, `uvm_file, `uvm_line); \
	// end
	//
	// `define uvm_warning(ID,MSG) \
	// begin \
	// if (uvm_report_enabled(UVM_NONE,UVM_WARNING,ID)) \
	// uvm_report_warning (ID, MSG, UVM_NONE, `uvm_file, `uvm_line); \
	// end
	//
	// `define uvm_error(ID,MSG) \
	// begin \
	// if (uvm_report_enabled(UVM_NONE,UVM_ERROR,ID)) \
	// uvm_report_error (ID, MSG, UVM_NONE, `uvm_file, `uvm_line); \
	// end
	//
	// `define uvm_fatal(ID,MSG) \
	// begin \
	// if (uvm_report_enabled(UVM_NONE,UVM_FATAL,ID)) \
	// uvm_report_fatal (ID, MSG, UVM_NONE, `uvm_file, `uvm_line); \
	// end

view raw uvm_info_vs_uvm_report_info.sv hosted with ❤ by GitHub

--------------------------------------------------------------------------------------------

How to change verbsity for particular component in UVM

There are two ways to set/control/change verbosity of particular component.

Using method call
Through Command line

Here I explained both using example.

Let's go through examples.

1. Using method call

-----------------------------------------------------------------------------------------------------

	`include "uvm.svh"
	import uvm_pkg::*;

	class rpting extends uvm_component;
	`uvm_component_utils(rpting)

	function new(string name,uvm_component parent);
	super.new(name, parent);
	endfunction : new

	task run();
	`uvm_info(get_full_name(),"Info Message : Verbo lvl - UVM_NONE ",UVM_NONE)
	`uvm_info(get_full_name(),"Info Message : Verbo lvl - UVM_LOW ",UVM_LOW)
	`uvm_info(get_full_name(),"Info Message : Verbo lvl - UVM_MEDIUM",UVM_MEDIUM)
	`uvm_warning(get_full_name(),"Warning Messgae from rpting")
	`uvm_error(get_full_name(),"Error Message from rpting \n\n")
	endtask : run
	endclass : rpting

	module top;
	rpting rpt1;
	rpting rpt2;
	rpting rpt3;
	initial begin
	rpt1 = new("rpt1",null);
	rpt2 = new("rpt2",null);
	rpt3 = new("rpt3",null);
	rpt1.set_report_verbosity_level(UVM_MEDIUM);
	rpt2.set_report_verbosity_level(UVM_LOW);
	rpt3.set_report_verbosity_level(UVM_NONE);
	run_test();
	end
	endmodule : top


	//Output:
	// UVM_INFO @ 0: reporter [RNTST] Running test ...
	// UVM_INFO top1.sv(19) @ 0: rpt1 [rpt1] Info Message : Verbo lvl - UVM_NONE
	// UVM_INFO top1.sv(20) @ 0: rpt1 [rpt1] Info Message : Verbo lvl - UVM_LOW
	// UVM_INFO top1.sv(21) @ 0: rpt1 [rpt1] Info Message : Verbo lvl - UVM_MEDIUM
	// UVM_WARNING top1.sv(22) @ 0: rpt1 [rpt1] Warning Messgae from rpting
	// UVM_ERROR top1.sv(23) @ 0: rpt1 [rpt1] Error Message from rpting
	//
	//
	// UVM_INFO top1.sv(19) @ 0: rpt2 [rpt2] Info Message : Verbo lvl - UVM_NONE
	// UVM_INFO top1.sv(20) @ 0: rpt2 [rpt2] Info Message : Verbo lvl - UVM_LOW
	// UVM_WARNING top1.sv(22) @ 0: rpt2 [rpt2] Warning Messgae from rpting
	// UVM_ERROR top1.sv(23) @ 0: rpt2 [rpt2] Error Message from rpting
	//
	//
	// UVM_INFO top1.sv(19) @ 0: rpt3 [rpt3] Info Message : Verbo lvl - UVM_NONE
	// UVM_WARNING top1.sv(22) @ 0: rpt3 [rpt3] Warning Messgae from rpting
	// UVM_ERROR top1.sv(23) @ 0: rpt3 [rpt3] Error Message from rpting

view raw set_verbosity_1.sv hosted with ❤ by GitHub

-----------------------------------------------------------------------------------------------------

2. Through Command line

-----------------------------------------------------------------------------------------------------

	`include "uvm.svh"
	import uvm_pkg::*;

	class my_env extends uvm_env;
	`uvm_component_utils(my_env)

	function new(string name,uvm_component parent);
	super.new(name, parent);
	endfunction : new

	task run();
	`uvm_info(get_full_name(),"Info Message : Verbo lvl - UVM_NONE ",UVM_NONE)
	`uvm_info(get_full_name(),"Info Message : Verbo lvl - UVM_LOW ",UVM_LOW)
	`uvm_info(get_full_name(),"Info Message : Verbo lvl - UVM_MEDIUM",UVM_MEDIUM)
	`uvm_warning(get_full_name(),"Warning Messgae from my_test")
	`uvm_error(get_full_name(),"Error Message from my_test \n\n")
	endtask : run
	endclass : my_env

	class my_test extends uvm_test;
	`uvm_component_utils(my_test)

	my_env env1, env2;

	function new(string name,uvm_component parent);
	super.new(name, parent);
	endfunction : new

	function void build_phase (uvm_phase phase);
	super.build_phase (phase);
	env1 = my_env :: type_id :: create ("env1", this);
	env2 = my_env :: type_id :: create ("env2", this);
	endfunction : build_phase

	task run();
	`uvm_info(get_full_name(),"Info Message : Verbo lvl - UVM_NONE ",UVM_NONE)
	`uvm_info(get_full_name(),"Info Message : Verbo lvl - UVM_LOW ",UVM_LOW)
	`uvm_info(get_full_name(),"Info Message : Verbo lvl - UVM_MEDIUM",UVM_MEDIUM)
	`uvm_warning(get_full_name(),"Warning Messgae from my_test")
	`uvm_error(get_full_name(),"Error Message from my_test \n\n")
	endtask : run
	endclass : my_test

	module top;
	initial begin
	run_test("my_test");
	end
	endmodule : top

view raw set_verbosity_2.sv hosted with ❤ by GitHub

	`include "uvm.svh"
	import uvm_pkg::*;

	class my_env extends uvm_env;
	`uvm_component_utils(my_env)

	function new(string name,uvm_component parent);
	super.new(name, parent);
	endfunction : new

	task run();
	`uvm_info(get_full_name(),"Info Message : Verbo lvl - UVM_NONE ",UVM_NONE)
	`uvm_info(get_full_name(),"Info Message : Verbo lvl - UVM_LOW ",UVM_LOW)
	`uvm_info(get_full_name(),"Info Message : Verbo lvl - UVM_MEDIUM",UVM_MEDIUM)
	`uvm_warning(get_full_name(),"Warning Messgae from my_test")
	`uvm_error(get_full_name(),"Error Message from my_test \n\n")
	endtask : run
	endclass : my_env

	class my_test extends uvm_test;
	`uvm_component_utils(my_test)

	my_env env1, env2;

	function new(string name,uvm_component parent);
	super.new(name, parent);
	endfunction : new

	function void build_phase (uvm_phase phase);
	super.build_phase (phase);
	env1 = my_env :: type_id :: create ("env1", this);
	env2 = my_env :: type_id :: create ("env2", this);
	endfunction : build_phase

	task run();
	`uvm_info(get_full_name(),"Info Message : Verbo lvl - UVM_NONE ",UVM_NONE)
	`uvm_info(get_full_name(),"Info Message : Verbo lvl - UVM_LOW ",UVM_LOW)
	`uvm_info(get_full_name(),"Info Message : Verbo lvl - UVM_MEDIUM",UVM_MEDIUM)
	`uvm_warning(get_full_name(),"Warning Messgae from my_test")
	`uvm_error(get_full_name(),"Error Message from my_test \n\n")
	endtask : run
	endclass : my_test

	module top;
	initial begin
	run_test("my_test");
	end
	endmodule : top

view raw set_verbosity_2.sv hosted with ❤ by GitHub

-----------------------------------------------------------------------------------------------------

Now run with 3 different simulation commands and see the difference.

+uvm_set_verbosity=component,id,verbosity,phase

-----------------------------------------------------------------------------------------------------

	// Simulation Command:
	// ./simv

	//Output:
	// UVM_INFO @ 0: reporter [RNTST] Running test my_test...
	// UVM_INFO top2.sv(19) @ 0: uvm_test_top.env1 [uvm_test_top.env1] Info Message : Verbo lvl - UVM_NONE
	// UVM_INFO top2.sv(20) @ 0: uvm_test_top.env1 [uvm_test_top.env1] Info Message : Verbo lvl - UVM_LOW
	// UVM_INFO top2.sv(21) @ 0: uvm_test_top.env1 [uvm_test_top.env1] Info Message : Verbo lvl - UVM_MEDIUM
	// UVM_WARNING top2.sv(22) @ 0: uvm_test_top.env1 [uvm_test_top.env1] Warning Messgae from my_test
	// UVM_ERROR top2.sv(23) @ 0: uvm_test_top.env1 [uvm_test_top.env1] Error Message from my_test
	//
	//
	// UVM_INFO top2.sv(19) @ 0: uvm_test_top.env2 [uvm_test_top.env2] Info Message : Verbo lvl - UVM_NONE
	// UVM_INFO top2.sv(20) @ 0: uvm_test_top.env2 [uvm_test_top.env2] Info Message : Verbo lvl - UVM_LOW
	// UVM_INFO top2.sv(21) @ 0: uvm_test_top.env2 [uvm_test_top.env2] Info Message : Verbo lvl - UVM_MEDIUM
	// UVM_WARNING top2.sv(22) @ 0: uvm_test_top.env2 [uvm_test_top.env2] Warning Messgae from my_test
	// UVM_ERROR top2.sv(23) @ 0: uvm_test_top.env2 [uvm_test_top.env2] Error Message from my_test
	//
	//
	// UVM_INFO top2.sv(43) @ 0: uvm_test_top [uvm_test_top] Info Message : Verbo lvl - UVM_NONE
	// UVM_INFO top2.sv(44) @ 0: uvm_test_top [uvm_test_top] Info Message : Verbo lvl - UVM_LOW
	// UVM_INFO top2.sv(45) @ 0: uvm_test_top [uvm_test_top] Info Message : Verbo lvl - UVM_MEDIUM
	// UVM_WARNING top2.sv(46) @ 0: uvm_test_top [uvm_test_top] Warning Messgae from my_test
	// UVM_ERROR top2.sv(47) @ 0: uvm_test_top [uvm_test_top] Error Message from my_test

	//-----------------------------------------------------------------------------------------------------

	//Simulation Command:
	// ./simv +uvm_set_verbosity=uvm_test_top,_ALL_,UVM_LOW,run +uvm_set_verbosity=uvm_test_top.env2,uvm_test_top.env2,UVM_NONE,run, +uvm_set_verbosity=uvm_test_top.env1,_ALL_,UVM_LOW,run

	//Output:
	// UVM_INFO @ 0: reporter [RNTST] Running test my_test...
	// UVM_INFO top2.sv(19) @ 0: uvm_test_top.env1 [uvm_test_top.env1] Info Message : Verbo lvl - UVM_NONE
	// UVM_INFO top2.sv(20) @ 0: uvm_test_top.env1 [uvm_test_top.env1] Info Message : Verbo lvl - UVM_LOW
	// UVM_WARNING top2.sv(22) @ 0: uvm_test_top.env1 [uvm_test_top.env1] Warning Messgae from my_test
	// UVM_ERROR top2.sv(23) @ 0: uvm_test_top.env1 [uvm_test_top.env1] Error Message from my_test
	//
	//
	// UVM_INFO top2.sv(19) @ 0: uvm_test_top.env2 [uvm_test_top.env2] Info Message : Verbo lvl - UVM_NONE
	// UVM_WARNING top2.sv(22) @ 0: uvm_test_top.env2 [uvm_test_top.env2] Warning Messgae from my_test
	// UVM_ERROR top2.sv(23) @ 0: uvm_test_top.env2 [uvm_test_top.env2] Error Message from my_test
	//
	//
	// UVM_INFO top2.sv(43) @ 0: uvm_test_top [uvm_test_top] Info Message : Verbo lvl - UVM_NONE
	// UVM_INFO top2.sv(44) @ 0: uvm_test_top [uvm_test_top] Info Message : Verbo lvl - UVM_LOW
	// UVM_WARNING top2.sv(46) @ 0: uvm_test_top [uvm_test_top] Warning Messgae from my_test
	// UVM_ERROR top2.sv(47) @ 0: uvm_test_top [uvm_test_top] Error Message from my_test

	//-----------------------------------------------------------------------------------------------------

	//Simulation Command:
	// ./simv ./simv +uvm_set_verbosity=*,_ALL_,UVM_LOW,run

	//Output:
	// UVM_INFO @ 0: reporter [RNTST] Running test my_test...
	// UVM_INFO top2.sv(19) @ 0: uvm_test_top.env1 [uvm_test_top.env1] Info Message : Verbo lvl - UVM_NONE
	// UVM_INFO top2.sv(20) @ 0: uvm_test_top.env1 [uvm_test_top.env1] Info Message : Verbo lvl - UVM_LOW
	// UVM_WARNING top2.sv(22) @ 0: uvm_test_top.env1 [uvm_test_top.env1] Warning Messgae from my_test
	// UVM_ERROR top2.sv(23) @ 0: uvm_test_top.env1 [uvm_test_top.env1] Error Message from my_test
	//
	//
	// UVM_INFO top2.sv(19) @ 0: uvm_test_top.env2 [uvm_test_top.env2] Info Message : Verbo lvl - UVM_NONE
	// UVM_INFO top2.sv(20) @ 0: uvm_test_top.env2 [uvm_test_top.env2] Info Message : Verbo lvl - UVM_LOW
	// UVM_WARNING top2.sv(22) @ 0: uvm_test_top.env2 [uvm_test_top.env2] Warning Messgae from my_test
	// UVM_ERROR top2.sv(23) @ 0: uvm_test_top.env2 [uvm_test_top.env2] Error Message from my_test
	//
	//
	// UVM_INFO top2.sv(43) @ 0: uvm_test_top [uvm_test_top] Info Message : Verbo lvl - UVM_NONE
	// UVM_INFO top2.sv(44) @ 0: uvm_test_top [uvm_test_top] Info Message : Verbo lvl - UVM_LOW
	// UVM_WARNING top2.sv(46) @ 0: uvm_test_top [uvm_test_top] Warning Messgae from my_test
	// UVM_ERROR top2.sv(47) @ 0: uvm_test_top [uvm_test_top] Error Message from my_test


	// _ALL_ is a "magic" name that can match either all severities or all IDs.

view raw set_verbosity_2_op.sv hosted with ❤ by GitHub

	// Simulation Command:
	// ./simv

	//Output:
	// UVM_INFO @ 0: reporter [RNTST] Running test my_test...
	// UVM_INFO top2.sv(19) @ 0: uvm_test_top.env1 [uvm_test_top.env1] Info Message : Verbo lvl - UVM_NONE
	// UVM_INFO top2.sv(20) @ 0: uvm_test_top.env1 [uvm_test_top.env1] Info Message : Verbo lvl - UVM_LOW
	// UVM_INFO top2.sv(21) @ 0: uvm_test_top.env1 [uvm_test_top.env1] Info Message : Verbo lvl - UVM_MEDIUM
	// UVM_WARNING top2.sv(22) @ 0: uvm_test_top.env1 [uvm_test_top.env1] Warning Messgae from my_test
	// UVM_ERROR top2.sv(23) @ 0: uvm_test_top.env1 [uvm_test_top.env1] Error Message from my_test
	//
	//
	// UVM_INFO top2.sv(19) @ 0: uvm_test_top.env2 [uvm_test_top.env2] Info Message : Verbo lvl - UVM_NONE
	// UVM_INFO top2.sv(20) @ 0: uvm_test_top.env2 [uvm_test_top.env2] Info Message : Verbo lvl - UVM_LOW
	// UVM_INFO top2.sv(21) @ 0: uvm_test_top.env2 [uvm_test_top.env2] Info Message : Verbo lvl - UVM_MEDIUM
	// UVM_WARNING top2.sv(22) @ 0: uvm_test_top.env2 [uvm_test_top.env2] Warning Messgae from my_test
	// UVM_ERROR top2.sv(23) @ 0: uvm_test_top.env2 [uvm_test_top.env2] Error Message from my_test
	//
	//
	// UVM_INFO top2.sv(43) @ 0: uvm_test_top [uvm_test_top] Info Message : Verbo lvl - UVM_NONE
	// UVM_INFO top2.sv(44) @ 0: uvm_test_top [uvm_test_top] Info Message : Verbo lvl - UVM_LOW
	// UVM_INFO top2.sv(45) @ 0: uvm_test_top [uvm_test_top] Info Message : Verbo lvl - UVM_MEDIUM
	// UVM_WARNING top2.sv(46) @ 0: uvm_test_top [uvm_test_top] Warning Messgae from my_test
	// UVM_ERROR top2.sv(47) @ 0: uvm_test_top [uvm_test_top] Error Message from my_test

	//-----------------------------------------------------------------------------------------------------

	//Simulation Command:
	// ./simv +uvm_set_verbosity=uvm_test_top,_ALL_,UVM_LOW,run +uvm_set_verbosity=uvm_test_top.env2,uvm_test_top.env2,UVM_NONE,run, +uvm_set_verbosity=uvm_test_top.env1,_ALL_,UVM_LOW,run

	//Output:
	// UVM_INFO @ 0: reporter [RNTST] Running test my_test...
	// UVM_INFO top2.sv(19) @ 0: uvm_test_top.env1 [uvm_test_top.env1] Info Message : Verbo lvl - UVM_NONE
	// UVM_INFO top2.sv(20) @ 0: uvm_test_top.env1 [uvm_test_top.env1] Info Message : Verbo lvl - UVM_LOW
	// UVM_WARNING top2.sv(22) @ 0: uvm_test_top.env1 [uvm_test_top.env1] Warning Messgae from my_test
	// UVM_ERROR top2.sv(23) @ 0: uvm_test_top.env1 [uvm_test_top.env1] Error Message from my_test
	//
	//
	// UVM_INFO top2.sv(19) @ 0: uvm_test_top.env2 [uvm_test_top.env2] Info Message : Verbo lvl - UVM_NONE
	// UVM_WARNING top2.sv(22) @ 0: uvm_test_top.env2 [uvm_test_top.env2] Warning Messgae from my_test
	// UVM_ERROR top2.sv(23) @ 0: uvm_test_top.env2 [uvm_test_top.env2] Error Message from my_test
	//
	//
	// UVM_INFO top2.sv(43) @ 0: uvm_test_top [uvm_test_top] Info Message : Verbo lvl - UVM_NONE
	// UVM_INFO top2.sv(44) @ 0: uvm_test_top [uvm_test_top] Info Message : Verbo lvl - UVM_LOW
	// UVM_WARNING top2.sv(46) @ 0: uvm_test_top [uvm_test_top] Warning Messgae from my_test
	// UVM_ERROR top2.sv(47) @ 0: uvm_test_top [uvm_test_top] Error Message from my_test

	//-----------------------------------------------------------------------------------------------------

	//Simulation Command:
	// ./simv ./simv +uvm_set_verbosity=*,_ALL_,UVM_LOW,run

	//Output:
	// UVM_INFO @ 0: reporter [RNTST] Running test my_test...
	// UVM_INFO top2.sv(19) @ 0: uvm_test_top.env1 [uvm_test_top.env1] Info Message : Verbo lvl - UVM_NONE
	// UVM_INFO top2.sv(20) @ 0: uvm_test_top.env1 [uvm_test_top.env1] Info Message : Verbo lvl - UVM_LOW
	// UVM_WARNING top2.sv(22) @ 0: uvm_test_top.env1 [uvm_test_top.env1] Warning Messgae from my_test
	// UVM_ERROR top2.sv(23) @ 0: uvm_test_top.env1 [uvm_test_top.env1] Error Message from my_test
	//
	//
	// UVM_INFO top2.sv(19) @ 0: uvm_test_top.env2 [uvm_test_top.env2] Info Message : Verbo lvl - UVM_NONE
	// UVM_INFO top2.sv(20) @ 0: uvm_test_top.env2 [uvm_test_top.env2] Info Message : Verbo lvl - UVM_LOW
	// UVM_WARNING top2.sv(22) @ 0: uvm_test_top.env2 [uvm_test_top.env2] Warning Messgae from my_test
	// UVM_ERROR top2.sv(23) @ 0: uvm_test_top.env2 [uvm_test_top.env2] Error Message from my_test
	//
	//
	// UVM_INFO top2.sv(43) @ 0: uvm_test_top [uvm_test_top] Info Message : Verbo lvl - UVM_NONE
	// UVM_INFO top2.sv(44) @ 0: uvm_test_top [uvm_test_top] Info Message : Verbo lvl - UVM_LOW
	// UVM_WARNING top2.sv(46) @ 0: uvm_test_top [uvm_test_top] Warning Messgae from my_test
	// UVM_ERROR top2.sv(47) @ 0: uvm_test_top [uvm_test_top] Error Message from my_test


	// _ALL_ is a "magic" name that can match either all severities or all IDs.

view raw set_verbosity_2_op.sv hosted with ❤ by GitHub

-----------------------------------------------------------------------------------------------------

Reference:

1. http://www.sunburst-design.com/papers/CummingsSNUG2014AUS_UVM_Messages.pdf

2. http://www.testbench.in/UT_03_UVM_REPORTING.html

import vs `include in SystemVerilog

The compiler goes through a pre-processor step. This step processes all the include files, conditionals, and text macros into a single stream of text. Except for error reporting and debugging, the compiler does not care how many files were used to make up that stream of text.

`include directive is just a mechanism for assembling text. The directive provides two key pieces of functionality:

Maintain repetitive blocks of text in a single file,
Specify file compilation order dependences from within a file instead of on the compiler command line,

SystemVerilog also supports separate compilation units. A compilation unit is one stream of text.

If you have multiple compiler command lines, then you will have at least one compilation unit per command line.

If you have multiple compilation units and have a set of classes that need to be shared across the compilation units, then you must use a package to define those classes or any user defined type.

And then in other compilation you can access that set of classes by importing that package.

Let’s go through one example,

1. Include

----------------------------------------------------------------------------------------------------------------------------------

	// File A.sv
	class A;
	int i;
	endclass : A


	// File P.sv
	package P;
	`include "A.sv"
	A a1;
	endpackage : P


	// File Q.sv
	package Q;
	`include "A.sv"
	A a1;
	endpackage : Q

view raw include_vs_import_1.sv hosted with ❤ by GitHub

-----------------------------------------------------------------------------------------------------------------------------------

After `including class A into each package, you wind up with two definitions of class A. Using `include is just a shortcut for cut and pasting text in a file. Importing a name from a package does not duplicate text; it makes that name visible from another package without copying the definition.

2. Import

-----------------------------------------------------------------------------------------------------------------------------------

	// File A.sv
	class A;
	int i;
	endclass : A


	// File P.sv
	package P;
	`include "A.sv"
	endpackage : P


	// File R.sv
	package R;
	import P::A;
	A a1;
	endpackage : R


	// File S.sv
	package S;
	import P::A;
	A a1;
	endpackage : S

view raw include_vs_import_2.sv hosted with ❤ by GitHub

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Class A is declared in package P, and only in package P. The variables R::a1 and S::a1 are type compatible because they are both of type P::A. The fact that class A was `included from another file once it is expanded is no longer relevant once you consider the placement of the text from the file.

Reference:

1. https://verificationacademy.com/forums/ovm/do-you-include-or-import

2. https://blogs.mentor.com/verificationhorizons/blog/2010/07/13/package-import-versus-include

Thursday, 4 February 2016

$unit vs $root in SystemVerilog

In one line you can say that, $unit represents the top level of each compilation unit, but $root refers to the top level instance.

Now let’s discuss it in little-bit more detail.

$root:

$root is the root of the instantiation tree.
SystemVerilog introduced the concept of $root as a global scope that allowed any kind of declaration (data types, classes, variables) along with module definitions nested in that global scope.
Any un-instantiated module is implicitly instantiated in $root.
A top-level module is implicitly instantiated once in $root, and its instance name is the same as the module name.

$unit:

A compilation unit formalizes a scope that represents what is visible in a compilation step – called $unit in SystemVerilog.
SystemVerilog borrowed the concept of packages from VHDL and standardized the concept of a compilation unit. A package allows you to compile definitions in a separate step and import those definitions into another compilation step.

Basic example of $unit,
-----------------------------------------------------------------------------------------------------------------

	string name = "Sagar";

	module mod();
	string name = "SSS";

	task print();
	$display( { "You've got 1 ", $unit::name, "!" } );
	$display( { "I've got 1 ", name, "!" } );
	$display( { "I've got 2 ", $root.mod.name, "!" } );
	endtask : print

	initial begin
	print();
	end
	endmodule

	//Output:
	// You've got 1 Sagar!
	// I've got 1 SSS!
	// I've got 2 SSS!

view raw unit_scope.sv hosted with ❤ by GitHub

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If you have a design that is compiled as a single compilation unit, there is really no conceptual difference between $unit and $root.

However, once you have a design with multiple compilation units, then $unit represents the top level of each compilation unit, and there is nothing in $root except for the implicitly instantiated module instances.

The only time you need to use $root or $unit is when a local name in the current scope hides a name in a higher level scope. For example,

-----------------------------------------------------------------------------------------------------------------

	// --------- Compilation unit 1 ----------
	// Contain only pkg1
	package pkg1;
	function void print;
	$display("comp1");
	endfunction : print
	endpackage : pkg1

	// --------- Compilation unit 2 ----------
	// Contain only pkg2
	package pkg2;
	function void print;
	$display("comp2");
	endfunction : print
	endpackage : pkg2


	// --------- Compilation unit 3 ----------
	// Contain task->print, module mod3, mod2, mod1
	// mod3 is instantiated in mod2.
	// mod2 is instantiated in mod1.
	// mod1 is not instantiated any where.
	// So, mod1 is implicitly instantiated in $root.
	function void print;
	$display("unit");
	endfunction : print

	module mod3();
	function void print;
	$display("mod3");
	endfunction : print
	endmodule : mod3

	module mod2();
	mod3 mod1(); // same name as top-level module
	function void print;
	$display("mod2");
	endfunction : print
	initial begin
	#5;
	$display($time," From initial block of module mod2");
	$root.mod1.print(); // prints "mod1"
	mod1.print(); // prints "mod3"
	pkg1::print(); // prints "comp1"
	pkg2::print(); // prints "comp2"
	$unit::print(); // prints "unit"
	end
	endmodule : mod2

	module mod1(); // top-level module
	mod2 m2();
	function void print;
	$display("mod1");
	endfunction : print
	initial begin
	#1;
	$display($time," From initial block of module mod1");
	print(); // prints "mod1"
	$root.mod1.print(); // prints "mod1"
	pkg1::print(); // prints "comp1"
	pkg2::print(); // prints "comp2"
	m2.print(); // prints "mod2"
	m2.mod1.print(); // prints "mod3"
	$unit::print(); // prints "unit"
	end
	endmodule : mod1

	//Output:
	// 1 From initial block of module mod1
	// mod1
	// mod1
	// comp1
	// comp2
	// mod2
	// mod3
	// unit
	// 5 From initial block of module mod2
	// mod1
	// mod3
	// comp1
	// comp2
	// unit

view raw unit_vs_root.sv hosted with ❤ by GitHub

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Here module “mod2” and module “mod1” has same task called “print”. The ambiguity is resolved by giving priority to the local scope and thereby preventing access to the top-level path. $root allows explicit access to the top level in those cases in which the name of the top-level module is insufficient to uniquely identify the path.

Note that there is no way for compilation unit 1 to directly refer to anything in compilation unit 2, or the other way around.

Reference:
1. https://blogs.mentor.com/verificationhorizons/blog/2009/09/25/unit-vs-root/