Callback in SystemVerilog

One of the main guidelines of this book is to create a single verifi cation environment that you can use for all tests with no changes. The key requirement is that this testbench must provide a “hook” where the test program can inject new code without modifying the original classes.

Your driver may want to do the following:

• Inject errors
• Drop the transaction
• Delay the transaction
• Put the transaction in the scoreboard
• Gather functional coverage data

Rather than try to anticipate every possible error, delay, or disturbance in the flow of transactions, the driver just needs to “call back” a method that is defined in the top-level test.
The beauty of this technique is that the callback method can be defined differently in every test. As a result, the test can add new functionality to the driver using callbacks, without editing the Driver class.
For some drastic behaviors such as dropping a transaction, you need to code this in the class ahead of time, but this is a known pattern. The reason why the transaction is dropped is left to the callback.

As shown in "Developer code" the Driver::run task loops forever with a call to a transmit task. Before sending the transaction, run calls the pre-transmit callback, if any. After sending the transaction, it calls the post-callback task, if any. By default, there are no callbacks, so run just calls transmit.

	//-------------------------------------------------------------------
	// Developer Code
	//-------------------------------------------------------------------
	// Transaction class
	class Transaction;
	rand bit [7:0] addr;
	rand logic [7:0] data;
	constraint addr_range_cn {
	addr inside {[10:20]};
	}
	constraint data_range_cn {
	data inside {[100:200]};
	}
	function string sprint();
	sprint = $sformatf("addr = %0d, data = %0d", addr, data);
	endfunction : sprint
	endclass : Transaction
	// Generator class
	class Generator;
	mailbox gen_drv;
	function new(input mailbox gen_drv);
	this.gen_drv = gen_drv;
	endfunction : new
	task run();
	Transaction tr;
	forever begin
	tr = new();
	if (!tr.randomize()) begin
	$fatal("time=%0t,Randomization Failed in Generator", $time);
	end
	else begin
	gen_drv.put(tr);
	$display("time=%0t, Generator : after randomization tr put in maibox = %s", $time, tr.sprint());
	end
	end
	endtask : run
	endclass : Generator
	// Driver_cbs class
	virtual class Driver_cbs; // Driver callbacks
	virtual task pre_tx(ref Transaction tr, ref bit drop);
	// By default, callback does nothing
	endtask : pre_tx
	virtual task post_tx(ref Transaction tr);
	// By default, callback does nothing
	endtask : post_tx
	endclass : Driver_cbs
	// Driver class
	class Driver;
	mailbox gen_drv;
	Driver_cbs cbs;
	function new(input mailbox gen_drv);
	this.gen_drv = gen_drv;
	endfunction : new
	task run();
	bit drop;
	Transaction tr;
	forever begin
	#1;
	drop = 0;
	// Get Transaction from Generator
	gen_drv.peek(tr);
	// pre_tx hook of callback
	cbs.pre_tx(tr, drop);
	if (drop == 1) begin
	gen_drv.get(tr); // Remove tr from mailbox
	$display("time=%0t, Driver : run : tr dropped, dropped tr = %s", $time, tr.sprint());
	continue;
	end
	// Actual transmit logic
	transmit(tr);
	// post_tx hook of callback
	cbs.post_tx(tr);
	end
	endtask : run
	task transmit(ref Transaction tr);
	$display("time=%0t, Driver : transmit : get tr from Generator = %s", $time, tr.sprint());
	#5; // Actual logic to drive value on interface
	gen_drv.get(tr);
	//$display("time=%0t, Driver : transmit : Value driven in interface", $time);
	endtask : transmit
	endclass : Driver
	//Agent class
	class Agent;
	mailbox gen_drv; //generator to driver mailbox
	Generator Gen;
	Driver Drv;
	function void build();
	gen_drv = new(1);
	Gen = new(gen_drv);
	Drv = new(gen_drv);
	endfunction : build
	task run();
	fork
	begin
	Gen.run();
	end
	begin
	Drv.run();
	end
	join_none
	endtask : run
	endclass : Agent

view raw sv_callback1.sv hosted with ❤ by GitHub

You could make Driver::run a virtual method and then override its behavior in an extended class, perhaps MyDriver::run. The drawback to this is that you might have to duplicate all the original method’s code in the new method if you are injecting new behavior. Now if you made a change in the base class, you would have to remember to propagate it to all the extended classes. Additionally, you can inject a callback without modifying the code that constructed the original object.

A callback task is created in the top-level test and called from the driver, the lowest level of the environment. However, the driver does not have to have any knowledge of the test – it just has to use a generic class that the test can extend.
 

	//------------------------------------------------------------------
	// End User Code 1
	//------------------------------------------------------------------
	// User defined extended callback class
	class Driver_cbs_drop extends Driver_cbs;
	virtual task pre_tx(ref Transaction tr, ref bit drop);
	bit _drop;
	// Randomly drop 1 out of every 5 transactions
	void'(std :: randomize(_drop) with {_drop inside {[0:4]};});
	drop = (_drop == 0);
	endtask : pre_tx
	endclass : Driver_cbs_drop
	// Test class
	class Test1;
	Agent Agt;
	Driver_cbs_drop cb;
	function void build();
	Agt = new();
	Agt.build();
	cb = new();
	Agt.Drv.cbs = this.cb;
	endfunction : build
	task run();
	fork
	Agt.run();
	join_none
	endtask:run
	endclass : Test1
	//Top module
	module top1();
	Test1 test;
	initial begin
	test = new();
	test.build();
	test.run();
	#40 $finish;
	end
	endmodule : top1
	//Output:
	// time=0, Generator : after randomization tr put in maibox = addr = 19, data = 189
	// time=1, Driver : run : tr dropped, dropped tr = addr = 19, data = 189
	// time=1, Generator : after randomization tr put in maibox = addr = 14, data = 112
	// time=2, Driver : transmit : get tr from Generator = addr = 14, data = 112
	// time=7, Generator : after randomization tr put in maibox = addr = 13, data = 115
	// time=8, Driver : transmit : get tr from Generator = addr = 13, data = 115
	// time=13, Generator : after randomization tr put in maibox = addr = 19, data = 135
	// time=14, Driver : transmit : get tr from Generator = addr = 19, data = 135
	// time=19, Generator : after randomization tr put in maibox = addr = 19, data = 138
	// time=20, Driver : run : tr dropped, dropped tr = addr = 19, data = 138
	// time=20, Generator : after randomization tr put in maibox = addr = 13, data = 133
	// time=21, Driver : run : tr dropped, dropped tr = addr = 13, data = 133
	// time=21, Generator : after randomization tr put in maibox = addr = 15, data = 136
	// time=22, Driver : run : tr dropped, dropped tr = addr = 15, data = 136
	// time=22, Generator : after randomization tr put in maibox = addr = 13, data = 127
	// time=23, Driver : run : tr dropped, dropped tr = addr = 13, data = 127
	// time=23, Generator : after randomization tr put in maibox = addr = 12, data = 200
	// time=24, Driver : transmit : get tr from Generator = addr = 12, data = 200
	// time=29, Generator : after randomization tr put in maibox = addr = 15, data = 104
	// time=30, Driver : transmit : get tr from Generator = addr = 15, data = 104
	// time=35, Generator : after randomization tr put in maibox = addr = 12, data = 176
	// time=36, Driver : transmit : get tr from Generator = addr = 12, data = 176

view raw sv_callback2.sv hosted with ❤ by GitHub

	//------------------------------------------------------------------
	// End User Code 2
	//------------------------------------------------------------------
	// User defined extended callback class
	class Driver_cbs_modify extends Driver_cbs;
	virtual task pre_tx(ref Transaction tr, ref bit drop);
	bit _modify;
	// Randomly drop 1 out of every 5 transactions
	void'(std :: randomize(_modify) with {_modify inside {[0:4]};});
	if (_modify == 0) begin
	tr.addr = tr.addr + 10;
	tr.data = tr.data + 10;
	$display("time=%0t, Driver_cbs_modify : modified tr = %s", $time, tr.sprint());
	end
	endtask : pre_tx
	endclass : Driver_cbs_modify
	// Test class
	class Test2;
	Agent Agt;
	Driver_cbs_modify cb;
	function void build();
	Agt = new();
	Agt.build();
	cb = new();
	Agt.Drv.cbs = this.cb;
	endfunction : build
	task run();
	fork
	Agt.run();
	join_none
	endtask:run
	endclass : Test2
	// Top module
	module top2();
	Test2 test;
	initial begin
	test = new();
	test.build();
	test.run();
	#40 $finish;
	end
	endmodule : top2
	//Output:
	// time=0, Generator : after randomization tr put in maibox = addr = 19, data = 189
	// time=1, Driver_cbs_modify : modified tr = addr = 29, data = 199
	// time=1, Driver : transmit : get tr from Generator = addr = 29, data = 199
	// time=6, Generator : after randomization tr put in maibox = addr = 14, data = 112
	// time=7, Driver : transmit : get tr from Generator = addr = 14, data = 112
	// time=12, Generator : after randomization tr put in maibox = addr = 13, data = 115
	// time=13, Driver : transmit : get tr from Generator = addr = 13, data = 115
	// time=18, Generator : after randomization tr put in maibox = addr = 19, data = 135
	// time=19, Driver : transmit : get tr from Generator = addr = 19, data = 135
	// time=24, Generator : after randomization tr put in maibox = addr = 19, data = 138
	// time=25, Driver_cbs_modify : modified tr = addr = 29, data = 148
	// time=25, Driver : transmit : get tr from Generator = addr = 29, data = 148
	// time=30, Generator : after randomization tr put in maibox = addr = 13, data = 133
	// time=31, Driver_cbs_modify : modified tr = addr = 23, data = 143
	// time=31, Driver : transmit : get tr from Generator = addr = 23, data = 143
	// time=36, Generator : after randomization tr put in maibox = addr = 15, data = 136
	// time=37, Driver_cbs_modify : modified tr = addr = 25, data = 146
	// time=37, Driver : transmit : get tr from Generator = addr = 25, data = 146

view raw sv_callback3.sv hosted with ❤ by GitHub

Limitations of SystemVerilog callback (w.r.t. uvm_callback).

• You cannot control particular nth number of transaction. Callback affects all the transaction or in random manner if you use randomization in extended callback as I had used in above both examples. For example you want initial some (n) transcation to drive without any modification, then for particular (n+1) transaction you want to modified its content. Then again for rest of all transaction you don't want any modification. This is not possible with SystemVerilog callback.
• You cannot Add or Delete callback runtime.

Difference between Variable and Signal in VHDL

Scope wise:
SIGNAL has scope to whole architecture. It can be access from any place in architecture of enitity.
VARIABLE is local t procedure defined in the architecture.

Behavior wise:
Variable assignment is evaluated and assigned in a single step:
1) Execution flow within the procedure is blocked until the Execution flow within the procedure is blocked until the
assignment is completed.
Variable assignment is same as Blocking assignment in Verilog.

Signal assignment is Evaluated and assigned in two steps:
1) The right The right-hand side is evaluated immediately.
2) The assignment to the left-hand side is postponed until other evaluations in the current time step are completed other evaluations in the current time step are completed.
Execution flow within the procedure continues until a timing control is encountered (flow is not blocked)
Signal assignment is same as Non-Blocking assignment in Verilog.
If several values are assigned to a given signal in one process, only the last assignment is effective.

Synthesis wise:
SIGNAL inter a FLOP during synthesis.
VARIABLE infer just a WIRE during synthesis.

Example:

Signal assignment:

	library IEEE;
	use IEEE.std_logic_1164.all;
	entity xor_sig is
	port (
	A, B, C: in STD_LOGIC;
	X, Y: out STD_LOGIC
	);
	end xor_sig;
	architecture SIG_ARCH of xor_sig is
	signal D: STD_LOGIC;
	signal E: STD_LOGIC;
	signal F: STD_LOGIC;
	begin
	SIG:process (A,B,C)
	begin
	D <= A; -- ignored !!
	E <= D xor F; -- OLD value of D is taken for right-hand side evaluation.
	F <= B xor D; -- OLD value of D is taken for right-hand side evaluation.
	X <= C xor E; -- OLD value of E is taken for right-hand side evaluation.
	D <= B; -- overrides !! After this timestamp value of D is equal to B.
	Y <= D xor F; -- OLD value of both D and F is taken for right-hand side evaluation.
	-- (During this assignment D don't has value of A or B)
	end process;
	end SIG_ARCH;

view raw vhdl_signal_vs_variable_1.vhd hosted with ❤ by GitHub

Variable assignment:

	library IEEE;
	use IEEE.std_logic_1164.all;
	use IEEE.std_logic_unsigned.all;
	entity xor_var is
	port (
	A, B, C: in STD_LOGIC;
	X, Y: out STD_LOGIC
	);
	end xor_var;
	architecture VAR_ARCH of xor_var is
	begin
	VAR:process (A,B,C)
	variable D: STD_LOGIC;
	variable E: STD_LOGIC;
	variable F: STD_LOGIC;
	variable P: STD_LOGIC;
	variable Q: STD_LOGIC;
	begin
	D := A; -- D is assigned with value of A.
	E := D xor F; -- NEW value of D is taken for right-hand side evaluation. (D has value of A)
	F := B xor D; -- NEW value of D is taken for right-hand side evaluation. (D has value of A)
	P := C xor E; -- NEW value of E is taken for right-hand side evaluation.
	D := B; -- Again value of D is changed. D is assigned with value of B.
	Q := D xor F; -- NEW value of both D and F is taken for right-hand side evaluation.
	-- (D has value of B, F has value of (B xor D(=A)))
	X <= P;
	Y <= Q;
	end process;
	end VAR_ARCH;

view raw vhdl_signal_vs_variable_2.vhd hosted with ❤ by GitHub

UVM_ERROR demoter code

	/*!
	* \brief report_catcher_err_info_demoter_c
	* UVM_ERROT to UVM_INFO Demoter, demote UVM_ERROR based on ID or MESSAGE of UVM_ERROR.
	*/
	class report_catcher_err_info_demoter_c #(int no_of_err_msg = 1,int no_of_err_id = 0) extends uvm_report_catcher;
	`uvm_object_utils(report_catcher_err_info_demoter_c)
	int unsigned no_of_err_msg_demoted[]; /*! \param */
	int unsigned no_of_err_id_demoted[]; /*! \param */
	string exp_err[]; /*! \param */
	string exp_id[]; /*! \param */
	int unsigned string_offset; /*! \param */
	//If we want that error should exactly the same as given, than make this bit 1
	bit exact_match_msg[]; /*! \param */
	/*!
	* \brief Constructor
	* Create a new transaction instance
	* \parameter: name - Instance name of the transaction
	*/
	extern function new(string name = "report_catcher_err_info_demoter_c");
	/*!
	* \brief Function pattern_match_f
	* Function used to match two string given as input arguments.
	* If string matches it will return 1 else return 0.
	* It is used to compare a message or ID of an error with
	* expected error message or ID.
	*/
	extern function bit pattern_match_f(
	input string str1, /*! \param string Output of get_message() or get_id() */
	input string str2, /*! \param string Actual string which is demoted */
	input bit ext_match, /*! \param bit used to represent exact_match_msg on/off */
	input int unsigned err_num, /*! \param int used to represent Err num */
	input bit msg_or_id /*! \param bit used to represent string is message or id, 1->msg, 0->id */
	);
	/*!
	* \brief Function catch
	* If severity is UVM_ERROR then change it to UVM_INFO.
	*/
	extern function action_e catch();
	endclass : report_catcher_err_info_demoter_c

view raw uvm_demoter1.sv hosted with ❤ by GitHub

-------------------------------------------------------------------------------------------------------------------------------

	function report_catcher_err_info_demoter_c::new(string name = "report_catcher_err_info_demoter_c");
	super.new(name);
	//dynamic array of size no_of_err_msg(no of error messages to be converted in to uvm_info)
	exp_err = new[no_of_err_msg];
	//dynamic array of size no_of_err_id(no of error messages to be converted in to uvm_info with help of error id)
	exp_id = new[no_of_err_id];
	no_of_err_msg_demoted = new[no_of_err_msg];
	no_of_err_id_demoted = new[no_of_err_id];
	exact_match_msg = new[no_of_err_msg];
	string_offset = 0;
	endfunction : new
	function bit report_catcher_err_info_demoter_c::pattern_match_f(
	input string str1,
	input string str2,
	input bit ext_match,
	input int unsigned err_num,
	input bit msg_or_id
	);
	int unsigned length_of_str1;
	int unsigned length_of_str2;
	bit match;
	length_of_str1 = str1.len();
	length_of_str2 = str2.len();
	`uvm_info(get_name(), $sformatf("length of str1=%0d, length of str2=%0d", length_of_str1, length_of_str2), UVM_HIGH)
	// Length comparision
	if (length_of_str2 == 0) // compare with null
	begin
	if (msg_or_id == 1'b1)
	begin
	`uvm_info(get_name(), $sformatf("Length of Expected Err message is ZERO, Doing nothing for err num %0d of err msg"), UVM_LOW)
	end
	else
	begin
	`uvm_info(get_name(), $sformatf("Length of Expected Err message is ZERO, Doing nothing for err num %0d of err id"), UVM_LOW)
	end
	return 0;
	end
	else if(ext_match == 0)
	begin
	//lenght of expected error message can be same or less than actual error message
	if(length_of_str2 > length_of_str1)
	begin
	return 0;
	end
	end
	else
	begin
	//length of expected error message and actual message should same
	if(length_of_str2 != length_of_str1)
	begin
	return 0;
	end
	end
	//for(int i = string_offset; i < length_of_str2 ; i++)
	for(int i = string_offset; i < (string_offset + length_of_str1 - length_of_str2 + 1) ; i++)
	begin
	if(str1.substr(i,i + length_of_str2 - 1) == str2)
	begin
	match = 1'b1;
	return 1;
	end
	end
	if (match == 1'b0)
	begin
	return 0;
	end
	endfunction : pattern_match_f

view raw uvm_demoter2.sv hosted with ❤ by GitHub

-------------------------------------------------------------------------------------------------------------------------------

	function action_e report_catcher_err_info_demoter_c::catch();
	//if(get_severity() == UVM_ERROR || get_severity() == UVM_INFO)
	if(get_severity() == UVM_ERROR)
	begin
	if(no_of_err_msg > 0)
	begin
	for(int i=0; i < no_of_err_msg; i++)
	begin
	if(pattern_match_f(.str1(get_message()), .str2(exp_err[i]), .ext_match(exact_match_msg[i]), .err_num(i), .msg_or_id(1))
	begin
	set_severity(UVM_INFO);
	set_action(UVM_NO_ACTION);
	set_verbosity(UVM_HIGH);
	no_of_err_msg_demoted[i] ++;
	end
	end
	end
	if(no_of_err_id > 0)
	begin
	for(int i=0; i < no_of_err_id; i++)
	begin
	if(pattern_match_f(.str1(get_id()), .str2(exp_id[i]), .ext_match(0), .err_num(i), .msg_or_id(0))
	begin
	set_severity(UVM_INFO);
	set_action(UVM_NO_ACTION);
	set_verbosity(UVM_HIGH);
	no_of_err_id_demoted[i] ++;
	end
	end
	end
	end
	return THROW;
	endfunction

view raw uvm_demoter3.sv hosted with ❤ by GitHub

Package in SystemVerilog

First Example:
--------------------------------------------------------------------------------------------------------------------------------

	package my_pkg1;
	int unsigned a = 1;
	endpackage : my_pkg1
	module top1();
	import my_pkg1 :: *;
	initial begin
	$display("my_pkg1::a = %0d", a);
	end
	endmodule : top1
	//Output:
	// my_pkg1::a = 1

view raw sv_pkg1.sv hosted with ❤ by GitHub

--------------------------------------------------------------------------------------------------------------------------------

Second Example:
--------------------------------------------------------------------------------------------------------------------------------

	package my_pkg1;
	int unsigned a = 1;
	endpackage : my_pkg1
	package my_pkg2;
	import my_pkg1 :: *;
	int unsigned b = 2;
	endpackage : my_pkg2
	module top2();
	//import my_pkg1 :: *;
	import my_pkg2 :: *;
	initial begin
	$display("top : my_pkg1::a = %0d, my_pkg2::b = %0d", a, b);
	end
	endmodule : top2
	//Output:
	// Identifier 'a' has not been declared yet. If this error is not expected, please check if you have set `default_nettype to none.

view raw sv_pkg2.sv hosted with ❤ by GitHub

--------------------------------------------------------------------------------------------------------------------------------

Third Example:
--------------------------------------------------------------------------------------------------------------------------------

	package my_pkg1;
	int unsigned a = 1;
	endpackage : my_pkg1
	package my_pkg2;
	import my_pkg1 :: *;
	int unsigned b = 2;
	endpackage : my_pkg2
	module top3();
	import my_pkg1 :: *;
	import my_pkg2 :: *;
	initial begin
	$display("top : my_pkg1::a = %0d, my_pkg2::b = %0d", a, b);
	end
	endmodule : top3
	//Output:
	// top : my_pkg1::a = 1, my_pkg2::b = 2

view raw sv_pkg3.sv hosted with ❤ by GitHub

--------------------------------------------------------------------------------------------------------------------------------
 
Fourth Example:
--------------------------------------------------------------------------------------------------------------------------------

	package my_pkg1;
	int unsigned a = 1;
	endpackage : my_pkg1
	package my_pkg2;
	import my_pkg1 :: *;
	int unsigned b = 2;
	function void pkg2_print();
	$display("my_pkg2 : pkg2_print : my_pkg1::a = %0d, my_pkg2::b = %0d", a, b);
	endfunction : pkg2_print
	endpackage : my_pkg2
	module top4();
	import my_pkg2 :: *;
	initial begin
	void '(pkg2_print());
	end
	endmodule : top4
	//Output:
	// my_pkg2 : pkg2_print : my_pkg1::a = 1, my_pkg2::b = 2

view raw sv_pkg4.sv hosted with ❤ by GitHub

--------------------------------------------------------------------------------------------------------------------------------

Fifth Example:
--------------------------------------------------------------------------------------------------------------------------------

	package my_pkg1;
	int unsigned a = 1;
	endpackage : my_pkg1
	package my_pkg2;
	import my_pkg1 :: *;
	int unsigned b = 2;
	function void pkg2_print();
	$display("my_pkg2 : pkg2_print : my_pkg1::a = %0d, my_pkg2::b = %0d", a, b);
	endfunction : pkg2_print
	endpackage : my_pkg2
	package my_pkg3;
	//import my_pkg1 :: *;
	import my_pkg2 :: *;
	int unsigned c = 3;
	function void pkg3_print();
	$display("my_pkg3 : pkg3_print : my_pkg1::a = %0d, my_pkg2::b = %0d, my_pkg3::c = %0d", a, b, c);
	endfunction : pkg3_print
	endpackage : my_pkg3
	module top5();
	import my_pkg3 :: *;
	initial begin
	void '(pkg3_print());
	end
	endmodule : top5
	//Output:
	// Identifier 'a' has not been declared yet. If this error is not expected, please check if you have set `default_nettype to none

view raw sv_pkg5.sv hosted with ❤ by GitHub

--------------------------------------------------------------------------------------------------------------------------------

Sixth Example:
--------------------------------------------------------------------------------------------------------------------------------

	package my_pkg1;
	int unsigned a = 1;
	endpackage : my_pkg1
	package my_pkg2;
	import my_pkg1 :: *;
	int unsigned b = 2;
	function void pkg2_print();
	$display("my_pkg2 : pkg2_print : my_pkg1::a = %0d, my_pkg2::b = %0d", a, b);
	endfunction : pkg2_print
	endpackage : my_pkg2
	package my_pkg3;
	import my_pkg1 :: *;
	import my_pkg2 :: *;
	int unsigned c = 3;
	function void pkg3_print();
	$display("my_pkg3 : pkg3_print : my_pkg1::a = %0d, my_pkg2::b = %0d, my_pkg3::c = %0d", a, b, c);
	endfunction : pkg3_print
	endpackage : my_pkg3
	module top6();
	import my_pkg3 :: *;
	initial begin
	void '(pkg3_print());
	end
	endmodule : top6
	//Output:
	// my_pkg3 : pkg3_print : my_pkg1::a = 1, my_pkg2::b = 2, my_pkg3::c = 3

view raw sv_pkg6.sv hosted with ❤ by GitHub

--------------------------------------------------------------------------------------------------------------------------------

Seventh Example:
--------------------------------------------------------------------------------------------------------------------------------

	package my_pkg1;
	int unsigned a = 1;
	endpackage : my_pkg1
	package my_pkg2;
	import my_pkg1 :: *;
	int unsigned b = 2;
	function void pkg2_print();
	$display("my_pkg2 : pkg2_print : my_pkg1::a = %0d, my_pkg2::b = %0d", a, b);
	endfunction : pkg2_print
	endpackage : my_pkg2
	package my_pkg3;
	//import my_pkg1 :: *;
	import my_pkg2 :: *;
	int unsigned c = 3;
	function void pkg3_print();
	$display("my_pkg3 : pkg3_print : my_pkg3::c = %0d", c);
	$display("calling my_pkg2 :: pkg2_print");
	pkg2_print();
	endfunction : pkg3_print
	endpackage : my_pkg3
	module top7();
	import my_pkg3 :: *;
	initial begin
	void '(pkg3_print());
	end
	endmodule : top7
	//Output:
	// my_pkg3 : pkg3_print : my_pkg3::c = 3
	// calling my_pkg2 :: pkg2_print
	// my_pkg2 : pkg2_print : my_pkg1::a = 1, my_pkg2::b = 2

view raw sv_pkg7.sv hosted with ❤ by GitHub

--------------------------------------------------------------------------------------------------------------------------------

Eighth Example: (package and module having variable with same name)

-------------------------------------------------------------------------------------------------------------------------------- 

	package my_pkg1;
	int unsigned a = 1;
	endpackage : my_pkg1
	module top();
	int unsigned a = 2;
	import my_pkg1 :: *;
	initial begin
	$display ("a=%0d", a);
	$display ("my_pkg1::a=%0d", my_pkg1::a);
	end
	endmodule : top
	//Output:
	// a=2
	// my_pkg1::a=1

view raw sv_pkg8.sv hosted with ❤ by GitHub

-------------------------------------------------------------------------------------------------------------------------------- 

Ninth Example: (package and module having variable with same name)

--------------------------------------------------------------------------------------------------------------------------------

	package my_pkg1;
	int unsigned a = 1;
	endpackage : my_pkg1
	module top();
	// Not importing my_pkg1 here
	int unsigned a = 2;
	initial begin
	$display ("a=%0d", a);
	$display ("my_pkg1::a=%0d", my_pkg1::a);
	end
	endmodule : top
	//Output:
	// a=2
	// my_pkg1::a=1

view raw sv_pkg9.sv hosted with ❤ by GitHub

--------------------------------------------------------------------------------------------------------------------------------

Semaphore in SystemVerilog

A semaphore allows you to control access to a resource.

Conceptually, a semaphore is a bucket. When a semaphore is allocated, a bucket that contains a fixed number of keys is created. Processes using semaphores must first procure a key from the bucket before they can continue to execute. If a specific process requires a key, only a fixed number of occurrences of that process can be in progress simultaneously. All others must wait until a sufficient number of keys are returned to the bucket.

Semaphores are typically used for mutual exclusion, access control to shared resources, and basic synchronization.

Imagine that you and your spouse share a car. Obviously, only one person can drive it at a time. You can manage this situation by agreeing that whoever has the key can drive it. When you are done with the car, you give up the car so that the other person can use it. The key is the semaphore that makes sure only one person has access to the car.

In operating system terminology, this is known as “mutually exclusive access,” so a semaphore is known as a “mutex” and is used to control access to a resource.

Semaphores can be used in a testbench when you have a resource, such as a bus, that may have multiple requestors from inside the testbench but, as part of the physical design, can only have one driver.

In SystemVerilog, a thread that requests a key when it is not available always blocks the execution of that particular thread. Multiple blocking threads are queued in FIFO order.

Semaphore is a built-in class that provides the following methods:

— Create a semaphore with a specified number of keys: new()

— Obtain one or more keys from the bucket: get()

— Return one or more keys into the bucket: put()

— Try to obtain one or more keys without blocking: try_get()

The default value for keyCount is 0.

If the specified number of keys is not available, the get() method blocks process until the keys become available.

If the specified number of keys is not available, the try_get() method returns 0.

	module top();
	semaphore sema = new(1); // Create semaphore with 1 key.
	initial begin
	repeat(3) begin
	fork
	////////// PROCESS 1 ////////////////
	begin
	$display("1: Waiting for key, time=%0t", $time);
	sema.get(1);
	$display("1: Got the Key, time=%0t", $time);
	#(10);// Do some work
	sema.put(1);
	$display("1: Returning back key, time=%0t", $time);
	#(10);
	end
	////////// PROCESS 2 ////////////////
	begin
	#1;
	$display("2: Waiting for Key, time=%0t", $time);
	sema.get(1);
	$display("2: Got the Key, time=%0t", $time);
	#(10);//Do some work
	sema.put(1);
	$display("2: Returning back key, time=%0t", $time);
	#(10);
	end
	join
	$display();
	end
	#1000;
	end
	endmodule : top

view raw semaphore.sv hosted with ❤ by GitHub

	//Output:
	// 1: Waiting for key, time=0
	// 1: Got the Key, time=0
	// 2: Waiting for Key, time=1
	// 1: Returning back key, time=10
	// 2: Got the Key, time=10
	// 2: Returning back key, time=20
	//
	// 1: Waiting for key, time=30
	// 1: Got the Key, time=30
	// 2: Waiting for Key, time=31
	// 1: Returning back key, time=40
	// 2: Got the Key, time=40
	// 2: Returning back key, time=50
	//
	// 1: Waiting for key, time=60
	// 1: Got the Key, time=60
	// 2: Waiting for Key, time=61
	// 1: Returning back key, time=70
	// 2: Got the Key, time=70
	// 2: Returning back key, time=80

view raw semaphore_output.sv hosted with ❤ by GitHub

Semaphores with Multiple Keys:

You can put more keys back than you took out. Suddenly you may have two keys but only one car!

Be careful if your testbench needs to get and put multiple keys. Perhaps you have one key left, and a thread requests two, causing it to block. Now a second thread requests a single semaphore – what should happen? In SystemVerilog the second request, get(1) , sneaks ahead of the earlier get(2) , bypassing the FIFO ordering.

Mailbox in SystemVerilog

How do you pass information between two threads? Perhaps your generator needs to create many transactions and pass them to a driver. You might be tempted to just have the generator thread call a task in the driver. If you do that, the generator needs to know the hierarchical path to the driver task, making your code less reusable. Additionally, this style forces the generator to run at the same speed as the driver, which can cause synchronization problems if one generator needs to control multiple drivers. The channel must allow its driver and receiver to operate asynchronously. You may be tempted to just use a shared array or queue, but it can be difficult to create threads that read, write, and blocks safely.

The solution is a SystemVerilog mailbox. From a hardware point of view, the easiest way to think about a mailbox is that it is just a FIFO, with a source and sink. The source puts data into the mailbox, and the sink gets values from the mailbox.

A mailbox is a communication mechanism that allows messages to be exchanged between processes. Data can be sent to a mailbox by one process and retrieved by another.

Conceptually, mailboxes behave like real mailboxes. When a letter is delivered and put into the mailbox, a person can retrieve the letter (and any data stored within). However, if the letter has not been delivered when the mailbox is checked, the person must choose whether to wait for the letter or to retrieve the letter on a subsequent trip to the mailbox. Similarly, SystemVerilog’s mailboxes provide processes to transfer and retrieve data in a controlled manner. Mailboxes are created as having either a bounded or unbounded queue size. A bounded mailbox becomes full when it contains the bounded number of messages. A process that attempts to place a message into a full mailbox shall be suspended until enough room becomes available in the mailbox queue. Unbounded mailboxes never suspend a thread in a send operation.

Mailbox is a built-in class that provides the following methods:

— Create a mailbox: new()

— Place a message in a mailbox: put()

— Try to place a message in a mailbox without blocking: try_put()

— Retrieve a message from a mailbox: get() or peek()

— Try to retrieve a message from a mailbox without blocking: try_get() or try_peek()

— Retrieve the number of messages in the mailbox: num()

A put() blocks if the mailbox is full, and get() blocks if the mailbox is empty.

Use try_put() if you want to see if the mailbox is full. And try_get() to see if it is empty. Both are non-blocking methods.

If they are successful, they return a nonzero value; otherwise, they return 0. In other words,

If the mailbox is full, the method try_put() returns 0.

If the mailbox is empty, then the method try_get() or try_peek() returns 0.

These are more reliable than the num() function, as the number of entries can change between when you measure it and when you next access the mailbox.

The peek() task gets a copy of the data in the mailbox but does not remove it.

The data is a single value, such as an integer, or logic of any size or a handle. A mailbox never contains objects, only references to them.

The default mailbox is typeless, that is, a single mailbox can send and receive any type of data. This is a very powerful mechanism, which, unfortunately, can also result in run-time errors due to type mismatches (types not equivalent) between a message and the type of the variable used to retrieve the message. Frequently, a mailbox is used to transfer a particular message type, and, in that case, it is useful to detect type mismatches at compile time.

	mailbox #(transaction) mb_tr; // Parameterized : Recommended
	mailbox mb_untyped; // Unspecialized : Not recommended (avoid)

view raw mailbox1.sv hosted with ❤ by GitHub

A classic mailbox bug:

A loop that randomizes objects and puts them in a mailbox, but the object is only constructed once, outside the loop. Since there is only one object, it is randomized over and over.

Below figure shows all the handles pointing to a single object. A mailbox only holds handles, not objects, so you end up with a mailbox containing multiple handles that all point to the single object. The code that gets the handles from the mailbox just sees the last set of random values.

	class transaction;
	rand bit [7:0] data;
	rand bit [7:0] addr;
	endclass : transaction
	class generator;
	task transmit_bad(input int unsigned n,
	input mailbox #(transaction) mb);
	transaction tr;
	tr = new();
	repeat (n) begin
	if (!tr.randomize()) begin
	$error("randomization failed");
	end
	else begin
	$display("GEN: transmit_bad: after randomization tr.addr=%0h, tr.data=%0h", tr.addr, tr.data);
	end
	mb.put(tr);
	end
	endtask : transmit_bad
	endclass : generator
	class driver;
	task receive_bad(input mailbox #(transaction) mb);
	transaction tr;
	forever begin
	#5ns;
	mb.get(tr);
	// drive tranaction to DUT
	$display("DRV: receive_bad: Received tr.addr=%0h, tr.data=%0h", tr.addr, tr.data);
	end
	endtask : receive_bad
	endclass : driver
	module top();
	generator gen;
	driver drv;
	mailbox #(transaction) mb;
	initial begin
	mb = new();
	gen = new();
	drv = new();
	// Run producer and Consumer in parallel
	fork
	begin
	gen.transmit_bad (5, mb);
	end
	begin
	drv.receive_bad(mb);
	end
	join
	end
	endmodule : top

view raw mailbox_bug.sv hosted with ❤ by GitHub

	//Output:
	// GEN: transmit_bad: after randomization tr.addr=26, tr.data=3
	// GEN: transmit_bad: after randomization tr.addr=f6, tr.data=e3
	// GEN: transmit_bad: after randomization tr.addr=0, tr.data=9e
	// GEN: transmit_bad: after randomization tr.addr=7a, tr.data=dd
	// GEN: transmit_bad: after randomization tr.addr=6f, tr.data=c2
	// DRV: receive_bad: Received tr.addr=6f, tr.data=c2
	// DRV: receive_bad: Received tr.addr=6f, tr.data=c2
	// DRV: receive_bad: Received tr.addr=6f, tr.data=c2
	// DRV: receive_bad: Received tr.addr=6f, tr.data=c2
	// DRV: receive_bad: Received tr.addr=6f, tr.data=c2

view raw mailbox_bug_output.sv hosted with ❤ by GitHub

The overcome this bug; make sure your loop has all three steps,
1) constructing the object,
2) randomizing it,
3) putting it in the mailbox

The result, shown in below figure, is that every handle points to a unique object. This type of generator is known as the Blueprint Pattern.

	class transaction;
	rand bit [7:0] data;
	rand bit [7:0] addr;
	endclass : transaction
	class generator;
	task transmit_good(input int unsigned n,
	input mailbox #(transaction) mb);
	transaction tr;
	repeat (n) begin
	// constructing the object
	tr = new();
	// randomizing object
	if (!tr.randomize()) begin
	$error("randomization failed");
	end
	else begin
	$display("GEN: transmit_good: after randomization tr.addr=%0h, tr.data=%0h", tr.addr, tr.data);
	end
	// putting object in the mailbox
	mb.put(tr);
	end
	endtask : transmit_good
	endclass : generator
	class driver;
	task receive_good(input mailbox #(transaction) mb);
	transaction tr;
	forever begin
	#5ns;
	mb.get(tr);
	// drive tranaction to DUT
	$display("DRV: receive: Received tr.addr=%0h, tr.data=%0h", tr.addr, tr.data);
	end
	endtask : receive_good
	endclass : driver
	module top();
	generator gen;
	driver drv;
	mailbox #(transaction) mb;
	initial begin
	mb = new();
	gen = new();
	drv = new();
	// Run producer and Consumer in parallel
	fork
	begin
	gen.transmit_good (5, mb);
	end
	begin
	drv.receive_good(mb);
	end
	join
	end
	endmodule : top

view raw mailbox_good.sv hosted with ❤ by GitHub

	//Output:
	// GEN: transmit_good: after randomization tr.addr=26, tr.data=3
	// GEN: transmit_good: after randomization tr.addr=5c, tr.data=76
	// GEN: transmit_good: after randomization tr.addr=27, tr.data=40
	// GEN: transmit_good: after randomization tr.addr=3f, tr.data=c9
	// GEN: transmit_good: after randomization tr.addr=eb, tr.data=99
	// DRV: receive: Received tr.addr=26, tr.data=3
	// DRV: receive: Received tr.addr=5c, tr.data=76
	// DRV: receive: Received tr.addr=27, tr.data=40
	// DRV: receive: Received tr.addr=3f, tr.data=c9
	// DRV: receive: Received tr.addr=eb, tr.data=99

view raw mailbox_good_output.sv hosted with ❤ by GitHub

Bounded Mailboxes:

By default, mailboxes are similar to an unlimited FIFO — a producer can put any number of objects into a mailbox before the consumer gets the objects out. However, you may want the two threads to operate in lockstep so that the producer blocks until the consumer is done with the object.

You can specify a maximum size for the mailbox when you construct it. The default mailbox size is 0 which creates an unbounded mailbox. Any size greater than 0 creates a bounded mailbox. If you attempt to put more objects than this limit, put() blocks until you get an object from the mailbox, creating a vacancy.

Synchronized Threads Using a Bounded Mailbox and a Peek:

In many cases, two threads that are connected by a mailbox should run in lockstep, so that the producer does not get ahead of the consumer. The benefit of this approach is that your entire chain of stimulus generation now runs in lock step.

To synchronize two threads, the Producer creates and puts a transaction into a mailbox, then blocks until the

Consumer finishes with it. This is done by having the Consumer remove the transaction from the mailbox only when it is finally done with it, not when the transaction is first detected.

Below example shows the first attempt to synchronize two threads, this time with a bounded mailbox. The Consumer uses the built-in mailbox method peek() to look at the data in the mailbox without removing. When the Consumer is done processing the data, it removes the data with get() . This frees up the Producer to generate a new value. If the Consumer loop started with a get() instead of the peek() , the transaction would be immediately removed from the mailbox, so the Producer could wake up before the Consumer finished with the transaction.

	class transaction;
	rand bit [7:0] data;
	rand bit [7:0] addr;
	endclass : transaction
	class generator;
	task transmit(input int unsigned n,
	input mailbox #(transaction) mb);
	transaction tr;
	repeat (n) begin
	// constructing the object
	tr = new();
	// randomizing object
	if (!tr.randomize()) begin
	$error("randomization failed");
	end
	else begin
	$display("GEN: transmit: after randomization tr.addr=%0h, tr.data=%0h", tr.addr, tr.data);
	end
	// putting object in the mailbox
	mb.put(tr);
	end
	endtask : transmit
	endclass : generator
	class driver;
	task receive(input mailbox #(transaction) mb);
	transaction tr;
	forever begin
	mb.peek(tr); // peek object from mailbox
	#5ns;
	$display("DRV: receiver: Received tr.addr=%0h, tr.data=%0h", tr.addr, tr.data);
	// drive tranaction to DUT
	mb.get(tr); // Remove object from mailbox
	end
	endtask : receive
	endclass : driver
	module top();
	generator gen;
	driver drv;
	mailbox #(transaction) mb;
	initial begin
	mb = new(1); // Bounded mailbox - limit=1
	gen = new();
	drv = new();
	// Run producer and Consumer in parallel
	fork
	begin
	gen.transmit (5, mb);
	end
	begin
	drv.receive(mb);
	end
	join
	end
	endmodule : top

view raw mailbox_sync.sv hosted with ❤ by GitHub

	//Output:
	// GEN: transmit: after randomization tr.addr=26, tr.data=3
	// GEN: transmit: after randomization tr.addr=5c, tr.data=76
	// DRV: receiver: Received tr.addr=26, tr.data=3
	// GEN: transmit: after randomization tr.addr=27, tr.data=40
	// DRV: receiver: Received tr.addr=5c, tr.data=76
	// GEN: transmit: after randomization tr.addr=3f, tr.data=c9
	// DRV: receiver: Received tr.addr=27, tr.data=40
	// GEN: transmit: after randomization tr.addr=eb, tr.data=99
	// DRV: receiver: Received tr.addr=3f, tr.data=c9
	// DRV: receiver: Received tr.addr=eb, tr.data=99

view raw mailbox_sync_output.sv hosted with ❤ by GitHub

You can see that the Producer and Consumer are in lockstep, but the Producer is still one transaction ahead of the Consumer. This is because a bounded mailbox with size=1 only blocks when you try to do a put of the second transaction.

Reference:
1) SystemVerilog for Verification 3rd edition, by Chris Spear

Randsequence in SystemVerilog

The random sequence generator is useful for randomly generating structured sequences of stimulus such as instructions or network traffic patterns.
By randomizing a packet, it will generate most unlikely scenarios which are not interested. These type of sequence of scenarios can be generated using randsequence.

randsequence is composed of one or more productions.
Each production contains a name and one or more production_list.
Production_list contains one or more production_item.
Production_items of production_list are further classified into terminals and non-terminals.
Non-terminals are defined in terms of terminals and other non-terminals.
A terminal is an indivisible item that needs no further definition than its associated code block.
Ultimately, every non-terminal is decomposed into its terminals.

	module rand_sequence1();
	initial begin
	repeat(5) begin
	randsequence( main )
	main : one two three ;
	one : {$write("one");};
	two : {$write(" two");};
	three: {$display(" three");};
	endsequence
	end
	end
	endmodule : rand_sequence1
	// Here production is "main".
	// production "main" contain only one production_list with 3 production_items named "one", "two", "three".
	// production_items "one", "two", "three" are terminals.
	// When the "main" is chosen, it will select the sequence "one", "two" and "three" in order.
	//Output:
	// one two three
	// one two three
	// one two three
	// one two three
	// one two three

view raw rand_sequence1.sv hosted with ❤ by GitHub

A single production can contain multiple production lists.
multiple production lists are separated by the | symbol.
Production lists separated by a | imply a set of choices, which the generator will make at random.

	module rand_sequence2();
	initial begin
	repeat(8) begin
	randsequence( main )
	main : one | two | three ;
	one : {$display("one");};
	two : {$display("two");};
	three: {$display("three");};
	endsequence
	end
	end
	endmodule : rand_sequence2
	// Here "main" is production,
	// "main" has 3 production_list, each production_list consist 1 production_item,
	// 1st production_list has a production_item called "one",
	// 2nd production_list has a production_item called "two",
	// 3rd production_list has a production_item called "three",
	// production_items "one", "two", "three" all are terminals.
	//Output:
	// three
	// three
	// one
	// two
	// three
	// two
	// two
	// one
	//Results show that one, two and three are selected randomly.

view raw rand_sequence2.sv hosted with ❤ by GitHub

By default procution_list is generated randomly, you can give probability for a production_list generation.
The probability that a production list is generated can be changed by assigning weights to production lists.
The probability that a particular production list is generated is proportional to its specified weight.
The := operator assigns the weight specified by the weight_specification to its production list.
A weight_specification must evaluate to an integral non-negative value.
Weight expressions are evaluated when their enclosing production is selected, thus allowing weights to change dynamically.

	module rand_sequence3();
	integer one_1,two_2,three_3;
	initial begin
	one_1 = 0;
	two_2 = 0;
	three_3 = 0;
	repeat(6000) begin
	randsequence( main )
	main : one := 1 | two := 2 | three := 3;
	one : {one_1++;};
	two : {two_2++;};
	three: {three_3++;};
	endsequence
	end
	$display(" one %0d \n two %0d \n three %0d",one_1,two_2,three_3);
	end
	endmodule : rand_sequence3
	//Output:
	// one 1044
	// two 1970
	// three 2986

view raw rand_sequence3.sv hosted with ❤ by GitHub

A production can be made conditional by means of an if..else production statement.
The expression can be any expression that evaluates to a boolean value. If the expression evaluates to true, the production following the expression is generated, otherwise the production following the optional else statement is generated.

	module rand_sequence4();
	integer one_1,two_2,three_3;
	reg on;
	initial begin
	on = 0;
	one_1 = 0;
	two_2 = 0;
	three_3 = 0;
	repeat(2500) begin
	randsequence( main )
	main : one three;
	one : {if(on) one_1++; else two_2 ++; };
	three: {three_3++;};
	endsequence
	end
	$display(" one %0d \n two %0d \n three %0d",one_1,two_2,three_3);
	end
	endmodule : rand_sequence4
	//Output:
	// one 0
	// two 2500
	// three 2500

view raw rand_sequence4.sv hosted with ❤ by GitHub

	module rand_sequence4a();
	integer one_1,two_2,three_3;
	reg on;
	initial begin
	on = 0;
	one_1 = 0;
	two_2 = 0;
	three_3 = 0;
	repeat(2500) begin
	randsequence( main )
	main : one three;
	one : if(on) incr_one else incr_two;
	incr_one : {one_1 += 2; one_1--;};
	incr_two : {two_2 += 2; two_2--;};
	three: {three_3++;};
	endsequence
	end
	$display(" one %0d \n two %0d \n three %0d",one_1,two_2,three_3);
	end
	endmodule : rand_sequence4a
	//Output:
	// one 0
	// two 2500
	// three 2500

view raw rand_sequence4a.sv hosted with ❤ by GitHub

A production can be selected from a set of alternatives using a case production statement.
The case expression is evaluated, and its value is compared against the value of each case-item expression, which are evaluated and compared in the order in which they are given.
The production associated with the first case-item expression that matches the case expression is generated.
If no matching case-item expression is found then the production associated with the optional default item is generated, or nothing if there no default item.
Case-item expressions separated by commas allow multiple expressions to share the production.

	module rand_sequence5();
	integer one_1,two_2,three_3;
	initial begin
	for(int i = 0 ;i < 10 ;i++)
	begin
	randsequence( main )
	main : case(i%3)
	0 : zero;
	1, 2 : non_zero;
	default : def;
	endcase;
	zero : {$display("zero");};
	non_zero : {$display("non_zero");};
	def : {$display("default");};
	endsequence
	end
	end
	endmodule : rand_sequence5
	//Output:
	// zero
	// non_zero
	// non_zero
	// zero
	// non_zero
	// non_zero
	// zero
	// non_zero
	// non_zero
	// zero

view raw rand_sequence5.sv hosted with ❤ by GitHub

The repeat production statement is used to iterate a production over a specified number of times.

	module rand_sequence6();
	integer one_1,two_2,three_3;
	initial begin
	one_1 = 0;
	two_2 = 0;
	three_3 = 0;
	repeat(6000) begin
	randsequence( main )
	main : one | repeat(2) two | repeat(3) three ;
	one : {one_1 ++; };
	two : {two_2 ++; };
	three: {three_3 ++; };
	endsequence
	end
	$display(" one %d \n two %d \n three %d",one_1,two_2,three_3);
	end
	endmodule : rand_sequence6
	//Output:
	// one 2059
	// two 4072
	// three 5715

view raw rand_sequence6.sv hosted with ❤ by GitHub

Randcase in SystemVerilog

randcase is a case statement that randomly selects one of its branches.

Randcase can be used in class or modules.

The randcase item expressions are non-negative integral values that constitute the branch weights.

An item weight divided by the sum of all weights gives the probability of taking that branch.

For example:

	randcase
	3 : x = 1;
	1 : x = 2;
	4 : x = 3;
	endcase

view raw randcase1.sv hosted with ❤ by GitHub

The sum of all weights is 8; therefore, the probability of taking the first branch is (3/8)0.375, the probability

of taking the second is (1/8)0.125, and the probability of taking the third is (4/8)0.5.

If a branch specifies a zero weight, then that branch is not taken.

If all randcase_items specify zero weights, then no branch is taken and a warning can be issued.

The randcase weights can be arbitrary expressions, not just constants.

For example:

	byte a, b;
	randcase
	a + b : x = 1;
	a - b : x = 2;
	a ^ ~b : x = 3;
	12'b800 : x = 4;
	endcase

view raw randcase2.sv hosted with ❤ by GitHub

In the preceding example, the first three weight expressions are computed using 8-bit precision, and the fourth

expression is computed using 12-bit precision.

The resulting weights are added as unsigned values using 12-bit precision. The weight selection then uses unsigned

12-bit comparison.

Each call to randcae statement will return a random number in the range from 0 to SUM.

$urandom_range(0,SUM) is used to generate a random number.

	module rand_case;
	integer x;
	integer cnt_1, cnt_2, cnt_3;
	initial begin
	cnt_1 = 0;
	cnt_2 = 0;
	cnt_3 = 0;
	repeat(100000) begin
	randcase
	3 : x = 1;
	1 : x = 2;
	4 : x = 3;
	endcase
	if(x == 1) begin
	cnt_1++;
	end
	else if(x == 2) begin
	cnt_2++;
	end
	else if(x ==3) begin
	cnt_3++;
	end
	end
	$display("count_1 = %0d, count_2 = %0d, count_3 = %0d", cnt_1, cnt_2, cnt_3);
	$display("Probability of count_1 = %0f, count_2 = %0f, count_3 = %0f", (cnt_1/100000.0), (cnt_2/100000.0), (cnt_3/100000.0));
	end
	endmodule : rand_case
	//Output:
	// count_1 = 37378, count_2 = 12480, count_3 = 50142
	// Probability of count_1 = 0.373780, count_2 = 0.124800, count_3 = 0.501420

view raw randcase3.sv hosted with ❤ by GitHub