Difference between rising_edge(clk) and (clk'event and clk='1') in VHDL

In VHDL there are two ways to find an edge transition of any signal (generally clock).

1. rising_edge(clk)
2. clk'event and clk = '1' 

So in this article I will explain the difference between rising_edge or falling_edge function and clk'event based edge detection. 

Example 1:

Result of Example 1:

 

Example 2:

Result of Example 2:

To get a clear view look at the rising_edge function as implemented in std_logic_1164 library:

As you can see the function returns a value "TRUE" only when the present value is '1' and the last value is '0'.If the past value is something like 'Z','U' etc. then it will return a "FALSE" value.This makes the code, bug free, beacuse the function returns only valid clock transitions,that means '0' to '1'.All the rules and examples said above equally apply to falling_edge() function also. 

But the statement (clk'event and clk='1') results TRUE when the present value is '1' and there is an edge transition in the clk.It doesnt see whether the previous value is '0' or not.