Different coding style of Flop/latch in VHDL

	-- Flop with Sync set/reset.
	process (clk)
	begin
	if (rising_edge(clk)) then
	if (rst1 = '0') then
	out1 <= '0';
	elsif (rst2 = '1') then
	out1 <= '1';
	else
	out1 <= in1;
	end if;
	end if;
	end process;
	-- Flop with multi Sync reset.
	process (clk)
	begin
	if (rising_edge(clk)) then
	if (rst1 = '0') then
	out2 <= '0';
	elsif (rst2 = '1') then
	out2 <= '0';
	else
	out2 <= in2;
	end if;
	end if;
	end process;
	-- Flop with Async set/reset
	process (clk, rst1, rst2)
	begin
	if (rst1 = '0') then
	out1 <= '0';
	else
	if (rst2 = '1') then
	out1 <= '1';
	else
	if (rising_edge(clk)) then
	out1 <= in1;
	end if;
	end if;
	end if;
	end process;
	-- Flop with multi Async reset
	process (clk, rst1, rst2)
	begin
	if (rst1 = '0') then
	out2 <= '0';
	else
	if (rst2 = '1') then
	out2 <= '0';
	else
	if (rising_edge(clk)) then
	out2 <= in2;
	end if;
	end if;
	end if;
	end process;
	-- Latch with Async set/reset
	process (clk, rst1, rst2)
	begin
	if(rst1 = '0') then
	out1 <= '0';
	elsif(rst2 = '1') then
	out1 <= '1';
	elsif (clk = '1') then
	out1 <= in1;
	end if;
	end process;
	-- Latch with multi Async reset
	process (clk, rst1, rst2)
	begin
	if (rst1 = '0' or rst2 = '1') then
	out2 <= '0';
	elsif (clk = '1') then
	out2 <= in2;
	end if;
	end process;
	-- Flop with Sync reset
	process (clk)
	begin
	if (rising_edge(clk)) then
	if (rst = '0') then
	out2 <= '0';
	else
	out2 <= in1;
	end if;
	end if;
	end process;

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