Difference between casex and casez

The case, casex and casez all do bit-wise comparisons between the selecting case expression and individual case item statements.

For casex and casez, comparisons are performed using the identity operator === instead of equality ==. casex ignores any bit position containing an X or Z; casez only ignores bit positions with a Z. 

Verilog literals use the both the  ? and z characters to represent the Z state.