Difference between casex and casez

The case, casex and casez all do bit-wise comparisons between the selecting case expression and individual case item statements.

For casex and casez, comparisons are performed using the identity operator === instead of equality ==. casex ignores any bit position containing an X or Z; casez only ignores bit positions with a Z. 

Verilog literals use the both the  ? and z characters to represent the Z state.

	// casex ignores any bit position containing an X or Z,
	// Verilog literals use the both the ? and z characters to represent the Z state
	module casex_example();
	reg [3:0] opcode;
	reg [1:0] a,b,c;
	reg [1:0] out;
	always @ (opcode or a or b or c)
	casex(opcode)
	4'b1zzx : begin // Don't care 2:0 bits
	out = a;
	$display($time," 4'b1zzx is selected, opcode %b",opcode);
	end
	4'b01?? : begin // bit 1:0 is don't care
	out = b;
	$display($time," 4'b01?? is selected, opcode %b",opcode);
	end
	4'b001? : begin // bit 0 is don't care
	out = c;
	$display($time," 4'b001? is selected, opcode %b",opcode);
	end
	default : begin
	$display($time," default is selected, opcode %b",opcode);
	end
	endcase
	// Testbench code goes here
	always #2 a = $random;
	always #2 b = $random;
	always #2 c = $random;
	initial begin
	opcode = 0;
	#2 opcode = 4'b101x;
	#2 opcode = 4'b1x1x;
	#2 opcode = 4'b1001;
	#2 opcode = 4'b0010;
	#2 opcode = 4'b01x1;
	#2 opcode = 4'b0000;
	#2 opcode = 4'b001z;
	#2 opcode = 4'b001x;
	#2 $finish;
	end
	endmodule
	//Output:
	// 0 default is selected, opcode 0000
	// 2 4'b1zzx is selected, opcode 101x
	// 4 4'b1zzx is selected, opcode 1x1x
	// 6 4'b1zzx is selected, opcode 1001
	// 8 4'b001? is selected, opcode 0010
	// 10 4'b01?? is selected, opcode 01x1
	// 12 default is selected, opcode 0000
	// 14 4'b001? is selected, opcode 001z
	// 16 4'b001? is selected, opcode 001x

view raw casex_ex.sv hosted with ❤ by GitHub

	// casez only ignores bit positions with a Z
	// Verilog literals use the both the ? and z characters to represent the Z state
	module casez_example();
	reg [3:0] opcode;
	reg [1:0] a,b,c;
	reg [1:0] out;
	always @ (opcode or a or b or c)
	casez(opcode)
	4'b1zzx : begin // Don't care about lower 2:1 bit, bit 0 match with x
	out = a;
	$display($time," 4'b1zzx is selected, opcode %b",opcode);
	end
	4'b01?? : begin // bit 1:0 is don't care
	out = b;
	$display($time," 4'b01?? is selected, opcode %b",opcode);
	end
	4'b001? : begin // bit 0 is don't care
	out = c;
	$display($time," 4'b001? is selected, opcode %b",opcode);
	end
	default : begin
	$display($time," default is selected, opcode %b",opcode);
	end
	endcase
	// Testbench code goes here
	always #2 a = $random;
	always #2 b = $random;
	always #2 c = $random;
	initial begin
	opcode = 0;
	#2 opcode = 4'b101x;
	#2 opcode = 4'b1x1x;
	#2 opcode = 4'b1001;
	#2 opcode = 4'b0010;
	#2 opcode = 4'b01x1;
	#2 opcode = 4'b0000;
	#2 opcode = 4'b001z;
	#2 opcode = 4'b001x;
	#2 $finish;
	end
	endmodule
	//Output:
	// 0 default is selected, opcode 0000
	// 2 4'b1zzx is selected, opcode 101x
	// 4 4'b1zzx is selected, opcode 1x1x
	// 6 default is selected, opcode 1001
	// 8 4'b001? is selected, opcode 0010
	// 10 4'b01?? is selected, opcode 01x1
	// 12 default is selected, opcode 0000
	// 14 4'b001? is selected, opcode 001z
	// 16 4'b001? is selected, opcode 001x

view raw casez_ex.sv hosted with ❤ by GitHub