Saturday, 23 January 2016

What is the difference between ‘0’ and “0” in VHDL?

In VHDL, the '0' (single quote) is a single bit when the signal type is std_logic or bit. If you declare:
     signal foo : std_logic_vector(7 downto 0);
and attempt the assignment:
    foo <= '0';
you'll get a compile-time error indicating a size mismatch. That's because you're trying to assign a one-bit value to an 8-bit vector. (NB: Verilog will happily sign-extend, or is it zero-extend? that single-bit into the full vector.)

For std_logic_vector, it represents a vector of only one bit. For example, the vector may be declared as std_logic_vector(0 downto 0).

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