What is the difference between ‘0’ and “0” in VHDL?

In VHDL, the '0' (single quote) is a single bit when the signal type is std_logic or bit. If you declare:

     signal foo : std_logic_vector(7 downto 0);

and attempt the assignment:

    foo <= '0';

you'll get a compile-time error indicating a size mismatch. That's because you're trying to assign a one-bit value to an 8-bit vector. (NB: Verilog will happily sign-extend, or is it zero-extend? that single-bit into the full vector.)

	library ieee;
	use ieee.std_logic_1164.all;
	entity core1 is
	end entity;
	architecture core1 of core1 is
	signal a : std_logic := '0';
	signal c : std_logic_vector (3 downto 0) := '0';
	begin
	end core1;

view raw vhdl_quote_1.vhd hosted with ❤ by GitHub

	--Outputs:
	-- Error-[ANL-EXPRTYP-MISMATCH] Expression type mismatch
	-- top.vhd, 11
	-- CORE1
	--
	-- signal c : std_logic_vector (3 downto 0) := '0';
	-- ^
	-- Expression is not of the required type. Expecting an expression of type
	-- STD_LOGIC_VECTOR declared in ARCHITECTURE CORE1.

view raw vhdl_quote_1_op.vhd hosted with ❤ by GitHub

	library ieee;
	use ieee.std_logic_1164.all;
	entity core1 is
	end entity;
	architecture core1 of core1 is
	signal a : std_logic := '0';
	signal c : std_logic_vector (3 downto 0) := "0";
	begin
	end core1;

view raw vhdl_quote_2.vhd hosted with ❤ by GitHub

	--Outputs:
	-- Error-[ANL-AGGR-STRLITSHORT] String literal too short
	-- top.vhd, 11
	-- CORE1
	--
	-- signal c : std_logic_vector (3 downto 0) := "0";
	-- ^
	-- Length of 1 is shorter than the expected length of 4.

view raw vhdl_quote_2_op.vhd hosted with ❤ by GitHub

	-- Compile free code
	library ieee;
	use ieee.std_logic_1164.all;
	entity core1 is
	end entity;
	architecture core1 of core1 is
	signal a : std_logic := '0';
	signal c : std_logic_vector (3 downto 0) := "0000";
	begin
	end core1;

view raw vhdl_quote_3.vhd hosted with ❤ by GitHub

For std_logic_vector, it represents a vector of only one bit. For example, the vector may be declared as std_logic_vector(0 downto 0).

	library ieee;
	use ieee.std_logic_1164.all;
	entity core1 is
	end entity;
	architecture core1 of core1 is
	signal a : std_logic := '0';
	signal c : std_logic_vector (0 downto 0) := '0';
	begin
	end core1;

view raw vhdl_quote_4.vhd hosted with ❤ by GitHub

	--Outputs:
	-- Error-[ANL-EXPRTYP-MISMATCH] Expression type mismatch
	-- top.vhd, 9
	-- CORE1
	--
	-- signal c : std_logic_vector (0 downto 0) := '0';
	-- ^
	-- Expression is not of the required type. Expecting an expression of type
	-- STD_LOGIC_VECTOR declared in ARCHITECTURE CORE1.

view raw vhdl_quote_4_op.vhd hosted with ❤ by GitHub

	-- Compile free code
	library ieee;
	use ieee.std_logic_1164.all;
	entity core1 is
	end entity;
	architecture core1 of core1 is
	signal a : std_logic := '0';
	signal c : std_logic_vector (0 downto 0) := "0";
	begin
	end core1;

view raw vhdl_quote_5.vhd hosted with ❤ by GitHub